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Newbie
Newbie
3,694 Views
Registered: ‎04-18-2012

Can't get interrupts to work on MicroBlaze IP Core

Hello,

I am using the microblaze ipcore (not with xps) and I can't find documentation about how to get the interrupts to work. This is what I came up with but it is not working

 

 


 

    u32 id = XPAR_IOMODULE_0_DEVICE_ID;
    XIOModule iomodule;

    XIOModule_Initialize(&iomodule, XPAR_IOMODULE_0_DEVICE_ID);

    XIOModule_Connect(&iomodule,
            XPAR_IOMODULE_0_SYSTEM_INTC_INTERRUPT_2_INTR,
            (XInterruptHandler) ISR,
            (void*) 0);

    XIOModule_Enable(&iomodule, XPAR_IOMODULE_0_SYSTEM_INTC_INTERRUPT_2_INTR);

    Xil_ExceptionInit();

    Xil_ExceptionRegisterHandler(XPAR_IOMODULE_0_DEVICE_ID,
            (Xil_ExceptionHandler) XIOModule_DeviceInterruptHandler,
            &id);

    Xil_ExceptionEnable();

    XIOModule_RegisterHandler(XPAR_IOMODULE_0_IO_BASEADDR,
            XPAR_SYSTEM_INTC_INTERRUPT_2_MASK,
            (XIOModule_Timer_Handler) ISR,
            (void*) 0);

    XIOModule_Start(&iomodule);


I am able to read and write on the GPIO and the UART of the module so it is started, but the interrupts won't fire.

 

Thanks a lot.

 

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3 Replies
Highlighted
3,610 Views
Registered: ‎08-09-2012

Re: Can't get interrupts to work on MicroBlaze IP Core

Hi,

Have you find a solution?

I'm very interested in!!

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Highlighted
Newbie
Newbie
3,573 Views
Registered: ‎08-23-2012

Re: Can't get interrupts to work on MicroBlaze IP Core

Hi

There are 2 ways to work with mb interrupts, using API or compiler language specific

Read

.http://chess.eecs.berkeley.edu/eecs149/documentation/th_ublaze_interrupts.pdf

or

Xilinx Embedded System Tools Reference Manual "Interrupt Management"

 

I have added som demo code

Hope it helps

/Frank

 

 

 

 

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Explorer
Explorer
2,993 Views
Registered: ‎02-17-2013

Re: Can't get interrupts to work on Arm zedboard custom peripheral

Hey 

I search example of application in c language which use interrupt with a custom peripheral. AI am interessed by the processor Arm of Zynq. 

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