Q: is there any reason why the ethernet MAC (ENET1) can't use the clock generated by the DDR PLL?
I have a design which works fine when the ENET1 uses the clock generated by the IO PLL. I'd like to reduce the power consumption by disabling the IO PLL (which would save ~110 mW). That implies that I must switch the ENET1 over to a different PLL (I selected the DDR PLL).
I generated projects with Vivado and the only modification is the GEM1_CLK_CTRL register (at address = 0xF8000144), which selects the clock source and divisors:
1- Using IO PLL (which generates a 1000 MHz clock):