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Observer
Observer
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Registered: ‎06-07-2012

Can't use DDR PLL for the clock to Ethernet 1?

Hello everyone,

 

Q: is there any reason why the ethernet MAC (ENET1) can't use the clock generated by the DDR PLL? 

 

I have a design which works fine when the ENET1 uses the clock generated by the IO PLL. I'd like to reduce the power consumption by disabling the IO PLL (which would save ~110 mW). That implies that I must switch the ENET1 over to a different PLL (I selected the DDR PLL).  

 

I generated projects with Vivado and the only modification is the GEM1_CLK_CTRL register (at address = 0xF8000144), which selects the clock source and divisors:

 

1- Using IO PLL  (which generates  a 1000 MHz clock):

GEM1_CLK_CTRL = 0x1008001  (activate ref clock, src=IO PLL, 1st divisor=8, 2nd divisor=1)

--> 1000 MHz / 8 = 125 MHz, appropriate for gigabit ethernet

 

2-Using DDR PLL  (which generates  a 1500 MHz clock):

GEM1_CLK_CTRL = 0x1008001  (activate ref clock, src=DDR PLL, 1st divisor=12, 2nd divisor=1)

--> 1500 MHz / 12 = 125 MHz, clock should be as previous configuration

 

Using the DDR PLL, I can still do register access to the PHY over MDIO but I'm not receiving any packets (which works fine when using IO PLL).

 

Did anyone else used a similar approach to reduce the power consumption on the Zynq's?

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Observer
Observer
2,621 Views
Registered: ‎06-07-2012

Re: Can't use DDR PLL for the clock to Ethernet 1?

Correction: when using DDR PLL: GEM1_CLK_CTRL = 0x100C31 (and not 0x1008001 which is a copy-paste error)
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