UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Contributor
Contributor
6,629 Views
Registered: ‎02-18-2015

Clock forwarding Microblaze Clock to pin - Oscillator clock VS. Microblaze clock

Jump to solution

Aloha to the Community,

I have a Spartan 6 - XC6LX45 FPGA and I am using Xilinx Platform Studio 14.7 for a project of mine. The onboard Oscillator is 24MHz and I want to implement a Microblaze with 100MHz clock frequency, that will be connected with my IP. Thus my IP will be clocked also at 100Mhz, through the Microblaze clock. I want also to forward the clock of the Microblaze to a pin of the FPGA, because I want it to route an IP that is implemented in another Kintex 7 FPGA (the FPGAs are interconnected). So in my user_logic.vhd file, I made a port to my IP (Spartan 6) and I passed to the port the clock of the Microblaze Bus2IP_Clk. The problem is that when I try to create the bitstream, the following errors pop up (ERROR:Place:1205 and ERROR:Place:1136):

INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
   (.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 17 secs 
Total CPU  time at the beginning of Placer: 17 secs 

Phase 1.1  Initial Placement Analysis
Phase 1.1  Initial Placement Analysis (Checksum:826d6d73) REAL time: 19 secs 

Phase 2.7  Design Feasibility Check
ERROR:Place:1205 - This design contains a global buffer instance,
   <clock_generator_0/clock_generator_0/PLL0_CLKOUT0_BUFG_INST>, driving the
   net, <clk_100_0000MHz>, that is driving the following (first 30) non-clock
   load pins off chip.
   < PIN: control_interface_0_lbus_clk_pin.O; >
   This design practice, in Spartan-6, can lead to an unroutable situation due
   to limitations in the global routing. If the design does route there may be
   excessive delay or skew on this net. It is recommended to use a Clock
   Forwarding technique to create a reliable and repeatable low skew solution:
   instantiate an ODDR2 component; tie the .D0 pin to Logic1; tie the .D1 pin to
   Logic0; tie the clock net to be forwarded to .C0; tie the inverted clock to
   .C1. If you wish to override this recommendation, you may use the
   CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
   this message to a WARNING and allow your design to continue. Although the net
   may still not route, you will be able to analyze the failure in FPGA_Editor.
   < PIN "clock_generator_0/clock_generator_0/PLL0_CLKOUT0_BUFG_INST.O"
   CLOCK_DEDICATED_ROUTE = FALSE; >

ERROR:Place:1136 - This design contains a global buffer instance,
   <clock_generator_0/clock_generator_0/PLL0_CLKOUT0_BUFG_INST>, driving the
   net, <clk_100_0000MHz>, that is driving the following (first 30) non-clock
   load pins.
   < PIN: control_interface_0_lbus_clk_pin.O; >
   This is not a recommended design practice in Spartan-6 due to limitations in
   the global routing that may cause excessive delay, skew or unroutable
   situations.  It is recommended to only use a BUFG resource to drive clock
   loads. If you wish to override this recommendation, you may use the
   CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
   this message to a WARNING and allow your design to continue.
   < PIN "clock_generator_0/clock_generator_0/PLL0_CLKOUT0_BUFG_INST.O"
   CLOCK_DEDICATED_ROUTE = FALSE; >

Phase 2.7  Design Feasibility Check (Checksum:826d6d73) REAL time: 20 secs 

Total REAL time to Placer completion: 20 secs 
Total CPU  time to Placer completion: 19 secs 
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

Mapping completed.
See MAP report file "PROJECT_X_v4_map.mrp" for details.
Problem encountered during the packing phase.

Design Summary
--------------
Number of errors   :   3
Number of warnings :  22
ERROR:Xflow - Program map returned error code 2. Aborting flow execution...
make: *** [__xps/PROJECT_X_v4_routed] Error 1
Done!
Overriding Xilinx file <TextEditor.cfg> with local file <C:/Xilinx/14.7/ISE_DS/EDK/data/TextEditor.cfg>


I have read many threads and the most helpfull were the following:
https://www.xilinx.com/support/answers/35032.html
https://www.xilinx.com/support/answers/41810.html
https://forums.xilinx.com/t5/General-Technical-Discussion/Random-Gated-Clock-warning/td-p/631892
https://forums.xilinx.com/t5/Spartan-Family-FPGAs/driving-clock-on-IO/td-p/212825
https://forums.xilinx.com/t5/Spartan-Family-FPGAs/how-to-instantiate-ODDR-block/td-p/232589

Now after enough reading I have the following questions:

a) Is it possible from an onboard 24Mhz Oscillator to create a Microblaze with 100MHz clock? Is that duty of the Clock Generator to automatically generate that 100MHz clock?

b) If I use the constraint < PIN "clock_generator_0/clock_generator_0/PLL0_CLKOUT0_BUFG_INST.O"
   CLOCK_DEDICATED_ROUTE = FALSE; > in my .UCF file, the problem seems to be solved and the bitstream is generated. Will that be a working practice? I mean, I am just passing an internal clock signal to a pin. That is practically a cable connected to a pin. How much delay or skew will be practically generated?

c) From the above links, I see that the answer to my problem is the use of an ODDR. The ODDR will route my internal clock signal to the pin, without any delay (according to https://www.xilinx.com/support/documentation/user_guides/ug382.pdf page 111). If I don't use an ODDR, will the clock arriving at the pin be phase shifted by 90 degrees?

 

d) How do I add an ODDR using XPS 14.7? If I have to write it my self, should I make it at my user_logic.vhd file?

The user_logic.vhd file is the following:

------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.            **
-- **                                                                       **
-- ** Xilinx, Inc.                                                          **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"         **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND       **
-- ** SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,        **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,        **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION           **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,     **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE      **
-- ** FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY              **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE               **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR        **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF       **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS       **
-- ** FOR A PARTICULAR PURPOSE.                                             **
-- **                                                                       **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename:          user_logic.vhd
-- Version:           4.00.a
-- Description:       User logic.
-- Date:              Sun Dec 04 20:07:15 2016 (by Create and Import Peripheral Wizard)
-- VHDL Standard:     VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
--   active low signals:                    "*_n"
--   clock signals:                         "clk", "clk_div#", "clk_#x"
--   reset signals:                         "rst", "rst_n"
--   generics:                              "C_*"
--   user defined types:                    "*_TYPE"
--   state machine next state:              "*_ns"
--   state machine current state:           "*_cs"
--   combinatorial signals:                 "*_com"
--   pipelined or register delay signals:   "*_d#"
--   counter signals:                       "*cnt*"
--   clock enable signals:                  "*_ce"
--   internal version of output port:       "*_i"
--   device pins:                           "*_pin"
--   ports:                                 "- Names begin with Uppercase"
--   processes:                             "*_PROCESS"
--   component instantiations:              "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------

-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;

-- DO NOT EDIT ABOVE THIS LINE --------------------

--USER libraries added here

------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
--   C_NUM_REG                    -- Number of software accessible registers
--   C_SLV_DWIDTH                 -- Slave interface data bus width
--
-- Definition of Ports:
--   Bus2IP_Clk                   -- Bus to IP clock
--   Bus2IP_Resetn                -- Bus to IP reset
--   Bus2IP_Data                  -- Bus to IP data bus
--   Bus2IP_BE                    -- Bus to IP byte enables
--   Bus2IP_RdCE                  -- Bus to IP read chip enable
--   Bus2IP_WrCE                  -- Bus to IP write chip enable
--   IP2Bus_Data                  -- IP to Bus data bus
--   IP2Bus_RdAck                 -- IP to Bus read transfer acknowledgement
--   IP2Bus_WrAck                 -- IP to Bus write transfer acknowledgement
--   IP2Bus_Error                 -- IP to Bus error response
------------------------------------------------------------------------------

entity user_logic is
  generic
  (
    -- ADD USER GENERICS BELOW THIS LINE ---------------
    --USER generics added here
    -- ADD USER GENERICS ABOVE THIS LINE ---------------

    -- DO NOT EDIT BELOW THIS LINE ---------------------
    -- Bus protocol parameters, do not add to or delete
    C_NUM_REG                      : integer              := 5;
    C_SLV_DWIDTH                   : integer              := 32
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
  );
  port
  (
    -- ADD USER PORTS BELOW THIS LINE ------------------
    --USER ports added here
	 lbus_clk: out std_logic;
	 lbus_rst: out std_logic;
	 lbus_a: out std_logic_vector (15 downto 0);
	 lbus_di: out std_logic_vector (15 downto 0);
	 lbus_wr: out std_logic;
	 lbus_rd: out std_logic;
	 lbus_do: in std_logic_vector (15 downto 0);
	 lbus_dvld: in std_logic;
	 dvld_out: out std_logic;
	 osc_inh_en: out std_logic;
    -- ADD USER PORTS ABOVE THIS LINE ------------------

    -- DO NOT EDIT BELOW THIS LINE ---------------------
    -- Bus protocol ports, do not add to or delete
    Bus2IP_Clk                     : in  std_logic;
    Bus2IP_Resetn                  : in  std_logic;
    Bus2IP_Data                    : in  std_logic_vector(C_SLV_DWIDTH-1 downto 0);
    Bus2IP_BE                      : in  std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
    Bus2IP_RdCE                    : in  std_logic_vector(C_NUM_REG-1 downto 0);
    Bus2IP_WrCE                    : in  std_logic_vector(C_NUM_REG-1 downto 0);
    IP2Bus_Data                    : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
    IP2Bus_RdAck                   : out std_logic;
    IP2Bus_WrAck                   : out std_logic;
    IP2Bus_Error                   : out std_logic
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
  );

  attribute MAX_FANOUT : string;
  attribute SIGIS : string;

  attribute SIGIS of Bus2IP_Clk    : signal is "CLK";
  attribute SIGIS of Bus2IP_Resetn : signal is "RST";

end entity user_logic;

------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------

architecture IMP of user_logic is

  --USER signal declarations added here, as needed for user logic
   component STD_FIFO is
		Generic (
			constant DATA_WIDTH  : positive := 16;
			constant FIFO_DEPTH	: positive := 256
		);
		Port ( 
			clk		: in  STD_LOGIC;
			rst		: in  STD_LOGIC;
			WriteEn	: in  STD_LOGIC;
			DataIn	: in  STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
			ReadEn	: in  STD_LOGIC;
			DataOut	: out STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
			Empty	: out STD_LOGIC;
			Full	: out STD_LOGIC
		);
	end component;
	
	component lbus_if_fsm is
		--generic ();
		
		port (	-------------- Clock and Reset
			clk: in std_logic;
			rst: in std_logic;
			-------------- Local Input/Output Bus
			lbus_comgen: in std_logic_vector (31 downto 0);
			lbus_indat: in std_logic_vector (15 downto 0);
			lbus_outdat: out std_logic_vector (15 downto 0);	
			lbus_status: out std_logic_vector (31 downto 0);
			input_enable: out std_logic:= '0';
			output_enable: out std_logic:= '0';
			osc_inh_en: out std_logic:= '1';
			-------------- Local Output Bus
			--lbus_clk: out std_logic;
			lbus_rst: out std_logic;
			lbus_a: out std_logic_vector (15 downto 0);
			lbus_di: out std_logic_vector (15 downto 0);
			lbus_wr: out std_logic;
			lbus_rd: out std_logic;
			lbus_do: in std_logic_vector (15 downto 0);
			lbus_dvld: in std_logic;
			dvld_out: out std_logic);
	end component;
	
	signal WriteEn_in:	std_logic; 
	signal ReadEn_in:	std_logic;
	signal WriteEn_out:	std_logic; 
	signal ReadEn_out:	std_logic;
	signal DataIn:		std_logic_vector (15 downto 0);
	signal DataOut:	std_logic_vector (15 downto 0);
	signal Empty_in:	std_logic;
	signal Full_in:	std_logic;
	signal Empty_out:	std_logic;
	signal Full_out: std_logic;
	
	signal lbus_comgen: std_logic_vector (31 downto 0);
	signal lbus_status: std_logic_vector (31 downto 0);	
	signal in_en:std_logic;
	signal out_en:std_logic;
	signal outfifo: std_logic_vector (15 downto 0);
	signal infifo: std_logic_vector (15 downto 0);
  ------------------------------------------
  -- Signals for user logic slave model s/w accessible register example
  ------------------------------------------
  signal slv_reg0                       : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
  signal slv_reg1                       : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
  signal slv_reg2                       : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
  signal slv_reg3                       : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
  signal slv_reg4                       : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
  signal slv_reg_write_sel              : std_logic_vector(4 downto 0);
  signal slv_reg_read_sel               : std_logic_vector(4 downto 0);
  signal slv_ip2bus_data                : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
  signal slv_read_ack                   : std_logic;
  signal slv_write_ack                  : std_logic;

begin

  --USER logic implementation added here

  ------------------------------------------
  -- Example code to read/write user logic slave model s/w accessible registers
  -- 
  -- Note:
  -- The example code presented here is to show you one way of reading/writing
  -- software accessible registers implemented in the user logic slave model.
  -- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
  -- to one software accessible register by the top level template. For example,
  -- if you have four 32 bit software accessible registers in the user logic,
  -- you are basically operating on the following memory mapped registers:
  -- 
  --    Bus2IP_WrCE/Bus2IP_RdCE   Memory Mapped Register
  --                     "1000"   C_BASEADDR + 0x0
  --                     "0100"   C_BASEADDR + 0x4
  --                     "0010"   C_BASEADDR + 0x8
  --                     "0001"   C_BASEADDR + 0xC
  -- 
  ------------------------------------------
  slv_reg_write_sel <= Bus2IP_WrCE(4 downto 0);
  slv_reg_read_sel  <= Bus2IP_RdCE(4 downto 0);
  slv_write_ack     <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4);
  slv_read_ack      <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4);

  -- implement slave model software accessible register(s)
  SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
  begin

    if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
      if Bus2IP_Resetn = '0' then
        slv_reg0 <= (others => '0');
  --      slv_reg1 <= (others => '0');
        slv_reg2 <= (others => '0');
  --      slv_reg3 <= (others => '0');
  --      slv_reg4 <= (others => '0');
      else
        case slv_reg_write_sel is
          when "10000" =>
            for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
              if ( Bus2IP_BE(byte_index) = '1' ) then
                slv_reg0(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
              end if;
            end loop;
--          when "01000" =>
--            for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
--              if ( Bus2IP_BE(byte_index) = '1' ) then
--                slv_reg1(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
--              end if;
--            end loop;
          when "00100" =>
            for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
              if ( Bus2IP_BE(byte_index) = '1' ) then
                slv_reg2(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
              end if;
            end loop;
--          when "00010" =>
--            for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
--              if ( Bus2IP_BE(byte_index) = '1' ) then
--                slv_reg3(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
--              end if;
--            end loop;
--          when "00001" =>
--            for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
--              if ( Bus2IP_BE(byte_index) = '1' ) then
--                slv_reg4(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
--              end if;
--            end loop;
          when others => null;
        end case;
      end if;
    end if;

  end process SLAVE_REG_WRITE_PROC;

  -- implement slave model software accessible register(s) read mux
  SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4 ) is
  begin

    case slv_reg_read_sel is
--      when "10000" => slv_ip2bus_data <= slv_reg0;
      when "01000" => slv_ip2bus_data <= slv_reg1;
--      when "00100" => slv_ip2bus_data <= slv_reg2;
      when "00010" => slv_ip2bus_data <= slv_reg3;
      when "00001" => slv_ip2bus_data <= slv_reg4;
      when others => slv_ip2bus_data <= (others => '0');
    end case;

  end process SLAVE_REG_READ_PROC;

  ------------------------------------------
  -- Example code to drive IP to Bus signals
  ------------------------------------------
  IP2Bus_Data  <= slv_ip2bus_data when slv_read_ack = '1' else
                  (others => '0');

  IP2Bus_WrAck <= slv_write_ack;
  IP2Bus_RdAck <= slv_read_ack;
  IP2Bus_Error <= '0';

  ------------------------------------------
  --USER defined Logic
  ------------------------------------------  
  WriteEn_in <= slv_reg_write_sel(4);	--Lasts for 1 clock cycle according to the timing diagramm	/ Writes to slv_reg0
  ReadEn_out <= slv_reg_read_sel(3);	--Lasts for 2 (or 1??) clock cycles according to the timing diagramm / Reads from slv_reg1
  
  
  DataIn <= slv_reg0(15 downto 0);
  lbus_comgen <= slv_reg2;
  
  G1: STD_FIFO port map (Bus2IP_Clk, Bus2IP_Resetn, WriteEn_in, DataIn, in_en, infifo, Empty_in, Full_in);
  G3: STD_FIFO port map (Bus2IP_Clk, Bus2IP_Resetn, out_en, outfifo, ReadEn_out, Dataout, Empty_out, Full_out);
  G2: lbus_if_fsm port map (Bus2IP_Clk, Bus2IP_Resetn, lbus_comgen, infifo, outfifo, lbus_status, in_en, out_en, osc_inh_en, lbus_rst, lbus_a, lbus_di, lbus_wr, lbus_rd, lbus_do, lbus_dvld, dvld_out);

  slv_reg3 <= lbus_status;
  slv_reg1 <= "0000000000000000"&DataOut;
  slv_reg4(0) <= Empty_in;
  slv_reg4(1) <= Full_in;
  slv_reg4(2) <= Empty_out;
  
  lbus_clk <= Bus2IP_Clk;
end IMP;

and the UCF file is the following:

#
# pin constraints
#
#
# additional constraints
#

NET "clock_generator_0_CLKIN_pin" TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz;


#================================================ Pin assignment
#------------------------------------------------ Clock, reset, LED, and SW.
#################
# CLOCK / RESET #
#################
NET "clock_generator_0_CLKIN_pin" LOC="M3" |IOSTANDARD=LVCMOS25;	
NET "control_interface_0_osc_inh_en_pin" LOC="M1" |IOSTANDARD=LVCMOS25 |SLEW="QUIETIO" |DRIVE=2 |TIG;

#NET "clk_ext_p0" LOC="D11" | IOSTANDARD=LVDS_25;
#NET "clk_ext_n0" LOC="C12" | IOSTANDARD=LVDS_25;
#NET "clk_ext_p1" LOC="C11" | IOSTANDARD=LVDS_25;
#NET "clk_ext_n1" LOC="A11" | IOSTANDARD=LVDS_25;

NET "RESET" LOC="M8" |IOSTANDARD=LVCMOS25 |TIG;	

#NET "wdt_wdi"   LOC="R9"  |IOSTANDARD=LVCMOS25 |SLEW="QUIETIO" |DRIVE=2 |TIG;
#NET "wdt_wdo_b" LOC="R22" |IOSTANDARD=LVCMOS15 |TIG ;

#------------------------------------------------ Local bus
############################################
# Kintex-7 HPIC (LVCMOS15, SSTL15 or HSTL) #
############################################

NET "control_interface_0_lbus_clk_pin" LOC="K21" |IOSTANDARD=LVCMOS15 |SLEW=QUIETIO |DRIVE=2;
NET "control_interface_0_lbus_dvld_pin" LOC="G22" |IOSTANDARD=LVCMOS15;

NET "control_interface_0_lbus_do_pin<0>"  LOC="D21" |IOSTANDARD=LVCMOS15 |SLEW=QUIETIO |DRIVE=2;	#P
NET "control_interface_0_lbus_do_pin<1>"  LOC="C19" |IOSTANDARD=LVCMOS15 |SLEW=QUIETIO |DRIVE=2;	#P
NET "control_interface_0_lbus_do_pin<2>"  LOC="B21" |IOSTANDARD=LVCMOS15 |SLEW=QUIETIO |DRIVE=2;	#P
NET "control_interface_0_lbus_do_pin<3>"  LOC="D19" |IOSTANDARD=LVCMOS15 |SLEW=QUIETIO |DRIVE=2;	#P
NET "control_interface_0_lbus_do_pin<4>"  LOC="C20" |IOSTANDARD=LVCMOS15 |SLEW=QUIETIO |DRIVE=2;	#P
NET "control_interface_0_lbus_do_pin<5>"  LOC="F18" |IOSTANDARD=LVCMOS15 |SLEW=QUIETIO |DRIVE=2;	#P
NET "control_interface_0_lbus_do_pin<6>"  LOC="A20" |IOSTANDARD=LVCMOS15 |SLEW=QUIETIO |DRIVE=2;	#P
NET "control_interface_0_lbus_do_pin<7>"  LOC="F21" |IOSTANDARD=LVCMOS15 |SLEW=QUIETIO |DRIVE=2;	#P
NET "control_interface_0_lbus_do_pin<8>"  LOC="K20" |IOSTANDARD=LVCMOS15 |SLEW=QUIETIO |DRIVE=2;	#P
NET "control_interface_0_lbus_do_pin<9>"  LOC="H21" |IOSTANDARD=LVCMOS15 |SLEW=QUIETIO |DRIVE=2;	#P
NET "control_interface_0_lbus_do_pin<10>" LOC="M20" |IOSTANDARD=LVCMOS15 |SLEW=QUIETIO |DRIVE=2;	#P
NET "control_interface_0_lbus_do_pin<11>" LOC="J20" |IOSTANDARD=LVCMOS15 |SLEW=QUIETIO |DRIVE=2;	#P
NET "control_interface_0_lbus_do_pin<12>" LOC="H20" |IOSTANDARD=LVCMOS15 |SLEW=QUIETIO |DRIVE=2;	#P
NET "control_interface_0_lbus_do_pin<13>" LOC="L20" |IOSTANDARD=LVCMOS15 |SLEW=QUIETIO |DRIVE=2;	#P
NET "control_interface_0_lbus_do_pin<14>" LOC="E20" |IOSTANDARD=LVCMOS15 |SLEW=QUIETIO |DRIVE=2;	#P
NET "control_interface_0_lbus_do_pin<15>" LOC="G19" |IOSTANDARD=LVCMOS15 |SLEW=QUIETIO |DRIVE=2;	#P

NET "control_interface_0_lbus_wr_pin" LOC="G20" |IOSTANDARD=LVCMOS15 |SLEW=QUIETIO |DRIVE=2;		#P
NET "control_interface_0_lbus_rd_pin" LOC="H19" |IOSTANDARD=LVCMOS15 |SLEW=QUIETIO |DRIVE=2;		#P
		
NET "control_interface_0_lbus_rst_pin" LOC="M21" |IOSTANDARD=LVCMOS15 |SLEW=QUIETIO |DRIVE=2;		#P

#NET "hpic_clk_p"    LOC="K21" |IOSTANDARD=DIFF_HSTL_I;
#NET "hpic_clk_n"    LOC="K22" |IOSTANDARD=DIFF_HSTL_I;

NET "control_interface_0_lbus_a_pin<0>"  LOC="D22" |IOSTANDARD=LVCMOS15;		#N
NET "control_interface_0_lbus_a_pin<1>"  LOC="B20" |IOSTANDARD=LVCMOS15;		#N
NET "control_interface_0_lbus_a_pin<2>"  LOC="B22" |IOSTANDARD=LVCMOS15;		#N
NET "control_interface_0_lbus_a_pin<3>"  LOC="D20" |IOSTANDARD=LVCMOS15;		#N
NET "control_interface_0_lbus_a_pin<4>"  LOC="C22" |IOSTANDARD=LVCMOS15;		#N
NET "control_interface_0_lbus_a_pin<5>"  LOC="F19" |IOSTANDARD=LVCMOS15;		#N
NET "control_interface_0_lbus_a_pin<6>"  LOC="A21" |IOSTANDARD=LVCMOS15;		#N
NET "control_interface_0_lbus_a_pin<7>"  LOC="F22" |IOSTANDARD=LVCMOS15;		#N
NET "control_interface_0_lbus_a_pin<8>"  LOC="K19" |IOSTANDARD=LVCMOS15;		#N
NET "control_interface_0_lbus_a_pin<9>"  LOC="H22" |IOSTANDARD=LVCMOS15;		#N
NET "control_interface_0_lbus_a_pin<10>" LOC="L19" |IOSTANDARD=LVCMOS15;		#N
NET "control_interface_0_lbus_a_pin<11>" LOC="J22" |IOSTANDARD=LVCMOS15;		#N
NET "control_interface_0_lbus_a_pin<12>" LOC="J19" |IOSTANDARD=LVCMOS15;		#N
NET "control_interface_0_lbus_a_pin<13>" LOC="L22" |IOSTANDARD=LVCMOS15;		#N
NET "control_interface_0_lbus_a_pin<14>" LOC="E22" |IOSTANDARD=LVCMOS15;		#N
NET "control_interface_0_lbus_a_pin<15>" LOC="F20" |IOSTANDARD=LVCMOS15;		#N


#NET "hpic_dq_n<17>" LOC="H18" |IOSTANDARD=LVCMOS15;
#NET "hpic_dq_n<18>" LOC="M22" |IOSTANDARD=LVCMOS15;

#######################################
# Kintex-7 HRIC (LVCMOS25 or LVDS_25) #
#######################################
NET "control_interface_0_lbus_di_pin<0>"  LOC="D9"  |IOSTANDARD=LVCMOS25;		#P
NET "control_interface_0_lbus_di_pin<1>"  LOC="C15" |IOSTANDARD=LVCMOS25;		#P
NET "control_interface_0_lbus_di_pin<2>"  LOC="E16" |IOSTANDARD=LVCMOS25;		#P
NET "control_interface_0_lbus_di_pin<3>"  LOC="B14" |IOSTANDARD=LVCMOS25;		#P
NET "control_interface_0_lbus_di_pin<4>"  LOC="C17" |IOSTANDARD=LVCMOS25;		#P
NET "control_interface_0_lbus_di_pin<5>"  LOC="D7"  |IOSTANDARD=LVCMOS25;		#P
NET "control_interface_0_lbus_di_pin<6>"  LOC="B16" |IOSTANDARD=LVCMOS25;		#P
NET "control_interface_0_lbus_di_pin<7>"  LOC="B6"  |IOSTANDARD=LVCMOS25;		#P
NET "control_interface_0_lbus_di_pin<8>"  LOC="B10" |IOSTANDARD=LVCMOS25;		#P
NET "control_interface_0_lbus_di_pin<9>"  LOC="B12" |IOSTANDARD=LVCMOS25;		#P
NET "control_interface_0_lbus_di_pin<10>" LOC="C7"  |IOSTANDARD=LVCMOS25;		#P
NET "control_interface_0_lbus_di_pin<11>" LOC="D14" |IOSTANDARD=LVCMOS25;		#P
NET "control_interface_0_lbus_di_pin<12>" LOC="D15" |IOSTANDARD=LVCMOS25;		#P
NET "control_interface_0_lbus_di_pin<13>" LOC="C13" |IOSTANDARD=LVCMOS25;		#P
NET "control_interface_0_lbus_di_pin<14>" LOC="D10" |IOSTANDARD=LVCMOS25;		#P
NET "control_interface_0_lbus_di_pin<15>" LOC="D6"  |IOSTANDARD=LVCMOS25;		#P

#------------------------------------------------ Other
#########
# OTHER #
#########
#NET "fan_pwm"    LOC="N19" |IOSTANDARD=LVCMOS15;
#NET "rsvio_p<0>" LOC="N6"  |IOSTANDARD=LVCMOS25;
#NET "rsvio_n<0>" LOC="N7"  |IOSTANDARD=LVCMOS25;

####################
# LX45 unused pins #
####################
CONFIG PROHIBIT="Y16";
CONFIG PROHIBIT="W15";
CONFIG PROHIBIT="T12";
CONFIG PROHIBIT="U12";
CONFIG PROHIBIT="T8";
CONFIG PROHIBIT="U8";
CONFIG PROHIBIT="T10";
CONFIG PROHIBIT="U10";
CONFIG PROHIBIT="W6";
CONFIG PROHIBIT="Y6";
CONFIG PROHIBIT="Y5";
CONFIG PROHIBIT="AB5";

#####################
# LX100 unused pins #
#####################
CONFIG PROHIBIT="D12";
CONFIG PROHIBIT="D13";
CONFIG PROHIBIT="E10";
CONFIG PROHIBIT="E12";
CONFIG PROHIBIT="E14";
CONFIG PROHIBIT="E8";
CONFIG PROHIBIT="F10";
CONFIG PROHIBIT="F12";
CONFIG PROHIBIT="F13";
CONFIG PROHIBIT="F14";
CONFIG PROHIBIT="F15";
CONFIG PROHIBIT="F8";
CONFIG PROHIBIT="F9";
CONFIG PROHIBIT="G11";
CONFIG PROHIBIT="G13";
CONFIG PROHIBIT="G8";
CONFIG PROHIBIT="G9";
CONFIG PROHIBIT="H10";
CONFIG PROHIBIT="H11";
CONFIG PROHIBIT="H12";
CONFIG PROHIBIT="H13";
CONFIG PROHIBIT="H14";


Thank you in advance for your help!

0 Kudos
1 Solution

Accepted Solutions
Contributor
Contributor
11,038 Views
Registered: ‎02-18-2015

Re: Clock forwarding Microblaze Clock to pin - Oscillator clock VS. Microblaze clock

Jump to solution

I found the solution to my problem and it is summed up in this really usefull and explainatory post of Mr. Avrum Warshawsky:

https://forums.xilinx.com/t5/Spartan-Family-FPGAs/Place-Error-1205-1136-1654-while-using-Clock-Wizard-generating/m-p/370877/highlight/true#M22673

I instantiated an ODDR2 from: Spartan 6 Libraries Guide f or HDL Designs (page 224), inside my user_logic.vhd file. Then I passed my Internal Clock to the input of the ODDR2 and I connected the output of the ODDR2, to the pin of the FPGA.
So the connection is like this: BUS2IP_Clk --> ODDR2 --> FPGA pin (OBUF).

No more errors (PLACE:1205 / PLACE:1136 / PACK:1654)!

6 Replies
Highlighted
Contributor
Contributor
6,603 Views
Registered: ‎02-18-2015

Re: Clock forwarding Microblaze Clock to pin - Oscillator clock VS. Microblaze clock

Jump to solution

I have instantiated an ODDR2 in my user_logic.vhd, and I am using it to pass the Bus2IP_Clk to my port which is connected to the FPGA pin. Now the file looks like this:

------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.            **
-- **                                                                       **
-- ** Xilinx, Inc.                                                          **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"         **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND       **
-- ** SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,        **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,        **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION           **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,     **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE      **
-- ** FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY              **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE               **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR        **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF       **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS       **
-- ** FOR A PARTICULAR PURPOSE.                                             **
-- **                                                                       **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename:          user_logic.vhd
-- Version:           4.00.a
-- Description:       User logic.
-- Date:              Sun Dec 04 20:07:15 2016 (by Create and Import Peripheral Wizard)
-- VHDL Standard:     VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
--   active low signals:                    "*_n"
--   clock signals:                         "clk", "clk_div#", "clk_#x"
--   reset signals:                         "rst", "rst_n"
--   generics:                              "C_*"
--   user defined types:                    "*_TYPE"
--   state machine next state:              "*_ns"
--   state machine current state:           "*_cs"
--   combinatorial signals:                 "*_com"
--   pipelined or register delay signals:   "*_d#"
--   counter signals:                       "*cnt*"
--   clock enable signals:                  "*_ce"
--   internal version of output port:       "*_i"
--   device pins:                           "*_pin"
--   ports:                                 "- Names begin with Uppercase"
--   processes:                             "*_PROCESS"
--   component instantiations:              "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------

-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
Library UNISIM;

use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

use UNISIM.vcomponents.all;

library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;

-- DO NOT EDIT ABOVE THIS LINE --------------------

--USER libraries added here

------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
--   C_NUM_REG                    -- Number of software accessible registers
--   C_SLV_DWIDTH                 -- Slave interface data bus width
--
-- Definition of Ports:
--   Bus2IP_Clk                   -- Bus to IP clock
--   Bus2IP_Resetn                -- Bus to IP reset
--   Bus2IP_Data                  -- Bus to IP data bus
--   Bus2IP_BE                    -- Bus to IP byte enables
--   Bus2IP_RdCE                  -- Bus to IP read chip enable
--   Bus2IP_WrCE                  -- Bus to IP write chip enable
--   IP2Bus_Data                  -- IP to Bus data bus
--   IP2Bus_RdAck                 -- IP to Bus read transfer acknowledgement
--   IP2Bus_WrAck                 -- IP to Bus write transfer acknowledgement
--   IP2Bus_Error                 -- IP to Bus error response
------------------------------------------------------------------------------

entity user_logic is
  generic
  (
    -- ADD USER GENERICS BELOW THIS LINE ---------------
    --USER generics added here
    -- ADD USER GENERICS ABOVE THIS LINE ---------------

    -- DO NOT EDIT BELOW THIS LINE ---------------------
    -- Bus protocol parameters, do not add to or delete
    C_NUM_REG                      : integer              := 5;
    C_SLV_DWIDTH                   : integer              := 32
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
  );
  port
  (
    -- ADD USER PORTS BELOW THIS LINE ------------------
    --USER ports added here
	 lbus_clk: out std_logic;
	 lbus_rst: out std_logic;
	 lbus_a: out std_logic_vector (15 downto 0);
	 lbus_di: out std_logic_vector (15 downto 0);
	 lbus_wr: out std_logic;
	 lbus_rd: out std_logic;
	 lbus_do: in std_logic_vector (15 downto 0);
	 lbus_dvld: in std_logic;
	 dvld_out: out std_logic;
	 osc_inh_en: out std_logic;
    -- ADD USER PORTS ABOVE THIS LINE ------------------

    -- DO NOT EDIT BELOW THIS LINE ---------------------
    -- Bus protocol ports, do not add to or delete
    Bus2IP_Clk                     : in  std_logic;
    Bus2IP_Resetn                  : in  std_logic;
    Bus2IP_Data                    : in  std_logic_vector(C_SLV_DWIDTH-1 downto 0);
    Bus2IP_BE                      : in  std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
    Bus2IP_RdCE                    : in  std_logic_vector(C_NUM_REG-1 downto 0);
    Bus2IP_WrCE                    : in  std_logic_vector(C_NUM_REG-1 downto 0);
    IP2Bus_Data                    : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
    IP2Bus_RdAck                   : out std_logic;
    IP2Bus_WrAck                   : out std_logic;
    IP2Bus_Error                   : out std_logic
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
  );

  attribute MAX_FANOUT : string;
  attribute SIGIS : string;

  attribute SIGIS of Bus2IP_Clk    : signal is "CLK";
  attribute SIGIS of Bus2IP_Resetn : signal is "RST";

end entity user_logic;

------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------

architecture IMP of user_logic is

  --USER signal declarations added here, as needed for user logic
   component STD_FIFO is
		Generic (
			constant DATA_WIDTH  : positive := 16;
			constant FIFO_DEPTH	: positive := 256
		);
		Port ( 
			clk		: in  STD_LOGIC;
			rst		: in  STD_LOGIC;
			WriteEn	: in  STD_LOGIC;
			DataIn	: in  STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
			ReadEn	: in  STD_LOGIC;
			DataOut	: out STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
			Empty	: out STD_LOGIC;
			Full	: out STD_LOGIC
		);
	end component;
	
	component lbus_if_fsm is
		--generic ();
		
		port (	-------------- Clock and Reset
			clk: in std_logic;
			rst: in std_logic;
			-------------- Local Input/Output Bus
			lbus_comgen: in std_logic_vector (31 downto 0);
			lbus_indat: in std_logic_vector (15 downto 0);
			lbus_outdat: out std_logic_vector (15 downto 0);	
			lbus_status: out std_logic_vector (31 downto 0);
			input_enable: out std_logic:= '0';
			output_enable: out std_logic:= '0';
			osc_inh_en: out std_logic:= '1';
			-------------- Local Output Bus
			--lbus_clk: out std_logic;
			lbus_rst: out std_logic;
			lbus_a: out std_logic_vector (15 downto 0);
			lbus_di: out std_logic_vector (15 downto 0);
			lbus_wr: out std_logic;
			lbus_rd: out std_logic;
			lbus_do: in std_logic_vector (15 downto 0);
			lbus_dvld: in std_logic;
			dvld_out: out std_logic);
	end component;
	
	-- ODDR2: Output Double Data Rate Output Register with Set, Reset 
	-- and Clock Enable.
	-- Spartan-6
	-- Xilinx HDL Libraries Guide, version 13.4
	ODDR2_inst : ODDR2
	generic map( 
			DDR_ALIGNMENT => "C0", -- Sets output alignment to "NONE", "C0", "C1" 
			INIT => '1', -- Sets initial state of the Q output to '0' or '1' 
			SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
	port map(
			Q => Q, -- 1-bit output data
			C0 => C0, -- 1-bit clock input
			C1 => C1, -- 1-bit clock input 
			CE => CE, -- 1-bit clock enable input
			D0 => D0, -- 1-bit data input (associated with C0)
			D1 => D1, -- 1-bit data input(associated with C1)
			R => R,-- 1-bit reset input
			S => S -- 1-bit set input
	);
	-- End of ODDR2_inst instantiation
	
	signal WriteEn_in:	std_logic; 
	signal ReadEn_in:	std_logic;
	signal WriteEn_out:	std_logic; 
	signal ReadEn_out:	std_logic;
	signal DataIn:		std_logic_vector (15 downto 0);
	signal DataOut:	std_logic_vector (15 downto 0);
	signal Empty_in:	std_logic;
	signal Full_in:	std_logic;
	signal Empty_out:	std_logic;
	signal Full_out: std_logic;
	
	signal lbus_comgen: std_logic_vector (31 downto 0);
	signal lbus_status: std_logic_vector (31 downto 0);	
	signal in_en:std_logic;
	signal out_en:std_logic;
	signal outfifo: std_logic_vector (15 downto 0);
	signal infifo: std_logic_vector (15 downto 0);
  ------------------------------------------
  -- Signals for user logic slave model s/w accessible register example
  ------------------------------------------
  signal slv_reg0                       : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
  signal slv_reg1                       : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
  signal slv_reg2                       : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
  signal slv_reg3                       : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
  signal slv_reg4                       : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
  signal slv_reg_write_sel              : std_logic_vector(4 downto 0);
  signal slv_reg_read_sel               : std_logic_vector(4 downto 0);
  signal slv_ip2bus_data                : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
  signal slv_read_ack                   : std_logic;
  signal slv_write_ack                  : std_logic;

begin

  --USER logic implementation added here

  ------------------------------------------
  -- Example code to read/write user logic slave model s/w accessible registers
  -- 
  -- Note:
  -- The example code presented here is to show you one way of reading/writing
  -- software accessible registers implemented in the user logic slave model.
  -- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
  -- to one software accessible register by the top level template. For example,
  -- if you have four 32 bit software accessible registers in the user logic,
  -- you are basically operating on the following memory mapped registers:
  -- 
  --    Bus2IP_WrCE/Bus2IP_RdCE   Memory Mapped Register
  --                     "1000"   C_BASEADDR + 0x0
  --                     "0100"   C_BASEADDR + 0x4
  --                     "0010"   C_BASEADDR + 0x8
  --                     "0001"   C_BASEADDR + 0xC
  -- 
  ------------------------------------------
  slv_reg_write_sel <= Bus2IP_WrCE(4 downto 0);
  slv_reg_read_sel  <= Bus2IP_RdCE(4 downto 0);
  slv_write_ack     <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4);
  slv_read_ack      <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4);

  -- implement slave model software accessible register(s)
  SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
  begin

    if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
      if Bus2IP_Resetn = '0' then
        slv_reg0 <= (others => '0');
  --      slv_reg1 <= (others => '0');
        slv_reg2 <= (others => '0');
  --      slv_reg3 <= (others => '0');
  --      slv_reg4 <= (others => '0');
      else
        case slv_reg_write_sel is
          when "10000" =>
            for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
              if ( Bus2IP_BE(byte_index) = '1' ) then
                slv_reg0(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
              end if;
            end loop;
--          when "01000" =>
--            for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
--              if ( Bus2IP_BE(byte_index) = '1' ) then
--                slv_reg1(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
--              end if;
--            end loop;
          when "00100" =>
            for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
              if ( Bus2IP_BE(byte_index) = '1' ) then
                slv_reg2(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
              end if;
            end loop;
--          when "00010" =>
--            for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
--              if ( Bus2IP_BE(byte_index) = '1' ) then
--                slv_reg3(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
--              end if;
--            end loop;
--          when "00001" =>
--            for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
--              if ( Bus2IP_BE(byte_index) = '1' ) then
--                slv_reg4(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
--              end if;
--            end loop;
          when others => null;
        end case;
      end if;
    end if;

  end process SLAVE_REG_WRITE_PROC;

  -- implement slave model software accessible register(s) read mux
  SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4 ) is
  begin

    case slv_reg_read_sel is
--      when "10000" => slv_ip2bus_data <= slv_reg0;
      when "01000" => slv_ip2bus_data <= slv_reg1;
--      when "00100" => slv_ip2bus_data <= slv_reg2;
      when "00010" => slv_ip2bus_data <= slv_reg3;
      when "00001" => slv_ip2bus_data <= slv_reg4;
      when others => slv_ip2bus_data <= (others => '0');
    end case;

  end process SLAVE_REG_READ_PROC;

  ------------------------------------------
  -- Example code to drive IP to Bus signals
  ------------------------------------------
  IP2Bus_Data  <= slv_ip2bus_data when slv_read_ack = '1' else
                  (others => '0');

  IP2Bus_WrAck <= slv_write_ack;
  IP2Bus_RdAck <= slv_read_ack;
  IP2Bus_Error <= '0';

  ------------------------------------------
  --USER defined Logic
  ------------------------------------------  
  WriteEn_in <= slv_reg_write_sel(4);	--Lasts for 1 clock cycle according to the timing diagramm	/ Writes to slv_reg0
  ReadEn_out <= slv_reg_read_sel(3);	--Lasts for 2 (or 1??) clock cycles according to the timing diagramm / Reads from slv_reg1
  
  DataIn <= slv_reg0(15 downto 0);
  lbus_comgen <= slv_reg2;
  
  G1: STD_FIFO port map (Bus2IP_Clk, Bus2IP_Resetn, WriteEn_in, DataIn, in_en, infifo, Empty_in, Full_in);
  G3: STD_FIFO port map (Bus2IP_Clk, Bus2IP_Resetn, out_en, outfifo, ReadEn_out, Dataout, Empty_out, Full_out);
  G2: lbus_if_fsm port map (Bus2IP_Clk, Bus2IP_Resetn, lbus_comgen, infifo, outfifo, lbus_status, in_en, out_en, osc_inh_en, lbus_rst, lbus_a, lbus_di, lbus_wr, lbus_rd, lbus_do, lbus_dvld, dvld_out);
  G4: ODDR2_inst port map (lbus_clk, Bus2IP_Clk, NOT(Bus2IP_Clk), '1', '1', '0', '0', '0')
  
  
  slv_reg3 <= lbus_status;
  slv_reg1 <= "0000000000000000"&DataOut;
  slv_reg4(0) <= Empty_in;
  slv_reg4(1) <= Full_in;
  slv_reg4(2) <= Empty_out;
  
  --lbus_clk <= Bus2IP_Clk;
end IMP;


Still, I get the same errors:

Running timing-driven placement...
Total REAL time at the beginning of Placer: 17 secs 
Total CPU  time at the beginning of Placer: 17 secs 

Phase 1.1  Initial Placement Analysis
Phase 1.1  Initial Placement Analysis (Checksum:826d6d73) REAL time: 19 secs 

Phase 2.7  Design Feasibility Check
ERROR:Place:1205 - This design contains a global buffer instance,
   <clock_generator_0/clock_generator_0/PLL0_CLKOUT0_BUFG_INST>, driving the
   net, <clk_100_0000MHz>, that is driving the following (first 30) non-clock
   load pins off chip.
   < PIN: control_interface_0_lbus_clk_pin.O; >
   This design practice, in Spartan-6, can lead to an unroutable situation due
   to limitations in the global routing. If the design does route there may be
   excessive delay or skew on this net. It is recommended to use a Clock
   Forwarding technique to create a reliable and repeatable low skew solution:
   instantiate an ODDR2 component; tie the .D0 pin to Logic1; tie the .D1 pin to
   Logic0; tie the clock net to be forwarded to .C0; tie the inverted clock to
   .C1. If you wish to override this recommendation, you may use the
   CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
   this message to a WARNING and allow your design to continue. Although the net
   may still not route, you will be able to analyze the failure in FPGA_Editor.
   < PIN "clock_generator_0/clock_generator_0/PLL0_CLKOUT0_BUFG_INST.O"
   CLOCK_DEDICATED_ROUTE = FALSE; >

ERROR:Place:1136 - This design contains a global buffer instance,
   <clock_generator_0/clock_generator_0/PLL0_CLKOUT0_BUFG_INST>, driving the
   net, <clk_100_0000MHz>, that is driving the following (first 30) non-clock
   load pins.
   < PIN: control_interface_0_lbus_clk_pin.O; >
   This is not a recommended design practice in Spartan-6 due to limitations in
   the global routing that may cause excessive delay, skew or unroutable
   situations.  It is recommended to only use a BUFG resource to drive clock
   loads. If you wish to override this recommendation, you may use the
   CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
   this message to a WARNING and allow your design to continue.
   < PIN "clock_generator_0/clock_generator_0/PLL0_CLKOUT0_BUFG_INST.O"
   CLOCK_DEDICATED_ROUTE = FALSE; >

Phase 2.7  Design Feasibility Check (Checksum:826d6d73) REAL time: 20 secs 

Total REAL time to Placer completion: 20 secs 
Total CPU  time to Placer completion: 20 secs 
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

Mapping completed.
See MAP report file "PROJECT_X_v4_map.mrp" for details.
Problem encountered during the packing phase.

Design Summary
--------------
Number of errors   :   3
Number of warnings :  22
ERROR:Xflow - Program map returned error code 2. Aborting flow execution...
make: *** [__xps/PROJECT_X_v4_routed] Error 1
Done!


Should I move the ODDR2 to another file, instead of the user_logic.hvd??
Please, I really need help with this!

0 Kudos
Contributor
Contributor
6,539 Views
Registered: ‎02-18-2015

Re: Clock forwarding Microblaze Clock to pin - Oscillator clock VS. Microblaze clock

Jump to solution

Please anyone that can point me to the right direction??

P.S. in the above VHDL, I forgot the";" at the end of component G4. I added it, but I am still getting the same errors.

0 Kudos
Contributor
Contributor
6,534 Views
Registered: ‎02-18-2015

Re: Clock forwarding Microblaze Clock to pin - Oscillator clock VS. Microblaze clock

Jump to solution

I am using the constrain "PIN "clock_generator_0/clock_generator_0/PLL0_CLKOUT0_BUFG_INST.O"    CLOCK_DEDICATED_ROUTE = FALSE;", in order to generate my bitstream. Either with ODDR2 or without it, the slack for CLKOUT0, remains the same.

How can I generate the bitstream without having to use the constraint? Should I move the instantiation and use of ODDR2, in another file?

Slack 1.JPG
Slack 2.JPG
0 Kudos
Contributor
Contributor
6,503 Views
Registered: ‎02-18-2015

Re: Clock forwarding Microblaze Clock to pin - Oscillator clock VS. Microblaze clock

Jump to solution

UP

0 Kudos
Contributor
Contributor
6,339 Views
Registered: ‎02-18-2015

Re: Clock forwarding Microblaze Clock to pin - Oscillator clock VS. Microblaze clock

Jump to solution

I used Chipscope and I am seeing that my lbus_clk port of the user_logic.vhd is always '0'. That means that BUS2IP_Clk doesn't pass through my port.
After reading this topic:
https://forums.xilinx.com/t5/Virtex-Family-FPGAs/Is-GCLK-pin-connected-to-IBUFG/td-p/114806

I assume that my connection should be,
BUS2IP_Clk --> BUFG --> ODDR2 --> my port

or

BUS2IP_Clk --> BUFG --> ODDR2 --> my port

inside the user_logic.vhd file.


Can anybody validate if any of the above is the correct way of passing my internal clock to a pin of the FPGA?

0 Kudos
Contributor
Contributor
11,039 Views
Registered: ‎02-18-2015

Re: Clock forwarding Microblaze Clock to pin - Oscillator clock VS. Microblaze clock

Jump to solution

I found the solution to my problem and it is summed up in this really usefull and explainatory post of Mr. Avrum Warshawsky:

https://forums.xilinx.com/t5/Spartan-Family-FPGAs/Place-Error-1205-1136-1654-while-using-Clock-Wizard-generating/m-p/370877/highlight/true#M22673

I instantiated an ODDR2 from: Spartan 6 Libraries Guide f or HDL Designs (page 224), inside my user_logic.vhd file. Then I passed my Internal Clock to the input of the ODDR2 and I connected the output of the ODDR2, to the pin of the FPGA.
So the connection is like this: BUS2IP_Clk --> ODDR2 --> FPGA pin (OBUF).

No more errors (PLACE:1205 / PLACE:1136 / PACK:1654)!