03-07-2019 08:50 AM
I have a Vivado block diagram design that I'm running on the ZCU102 board. I started with the 10G Ethernet reference design.
I added a Clocking Wizard IP to my design and connect the pl_clk0 clock from the Zynq_ultra_ps_e_0 block. pl_clk0 is configured to run at 125MHz. Double clicking on the Clocking Wizard block to open the GUI, on the clocking options tab, under input clock information, clk_in1 frequency is greyed out (indicating it is autopopulated) and shows 100MHz.
I think it should show 125MHz? But I don't know if it only updates after the fact, or just doesn't show, so I go ahead to specifying the output.
I want my MMCM/PLL to output at 250, so I set the output frequency to 250MHz, and on the PLL Settings page it shows CLKFBOUT_MOUT as 10, and Divide as 4. These values are what I would expect to generate a 250MHz clock from a 100MHz clock; i.e: 100*10/4 = 250.
Not what I would expect to generate a 250 MHz from a 125MHz clock, Mult by 2, Divide by 1
I have several hierarchies in my block diagram. Which means that I have a Top Level block and inside it is another within which the clocking wizard lives, but I've tried moving the clokcing wizard block, and even if I connect it directly to the PL) pin on the Zynq BLock, it doesn't want to pick up the 125MHz frequency.
Has anyone had this or a similar problem?
03-07-2019 09:10 AM
I went ahead and clicked generate Block Design, and when I subsquently went back to the GUI, it showed the correct 124.XXX frequency. IIRC, the clocking wizard has been around since pre vivado, so it's possible that the way it picks up values is subtlely different from the rest of the IP Stuff?
03-09-2019 01:58 AM
I assume you had the input clock already connected. Sometimes it takes a Validate design to propagate the signal properties like the clock frequency.