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Adventurer
Adventurer
12,834 Views
Registered: ‎12-26-2013

Communication between the 2 ARM Cortex A9?

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Hi,

 

I'm working on zedboard and I want to use the dual core ARM cortexA9 for my system.

 

Under SDK, i have created two projects, one for ARM0 and the second for ARM1. I want to know how to communicate this two ARMs using DDR memory.

 

 

Can you help me please.

Thank you in advance.

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1 Solution

Accepted Solutions
Scholar trenz-al
Scholar
20,059 Views
Registered: ‎11-09-2013

Re: Communication between the 2 ARM Cortex A9?

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DDR memory is usually cached, are you sure that the data written by one CPU that goes to write cache

is instantly visible in the read cache of the other?

 

thats why I suggested using OCM at FFFF0000 for mailboxes

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11 Replies
Xilinx Employee
Xilinx Employee
12,823 Views
Registered: ‎07-01-2010

Re: Communication between the 2 ARM Cortex A9?

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Hi ,

The XAPP 1079 has information you are looking for.


DDR memory sharing from XAPP:


DDR memory: CPU0 has only been made aware of memory at 0x00100000 to
0x001FFFFF. CPU1 uses memory from 0x00200000 to 0x002FFFFF for its bare-metal
application.

http://www.xilinx.com/support/documentation/application_notes/xapp1079-amp-bare-metal-cortex-a9.pdf

Regards,
Achutha

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Scholar trenz-al
Scholar
12,813 Views
Registered: ‎11-09-2013

Re: Communication between the 2 ARM Cortex A9?

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SEPARATING the DDR memory does SEPARATE the two CPUs, and do not help the OP he wanted to have communication between the CPUs.

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Adventurer
Adventurer
12,775 Views
Registered: ‎12-26-2013

Re: Communication between the 2 ARM Cortex A9?

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Hi, 

 

 

Thank you for your response.

In the XAPP 1079,  it is mentioned that we can use FSBL application to boot the design, then Copying Boot File to SD Card.

But in my case, I don't need to use a bootable solution. 

 

I tried to run two bare-metal applications for CPU0 and CPU1 sharing the DDR memory under SDK, as follows :

 

Project ARM0: it writes some data in the DDR memory :

 

#include <stdio.h>
#include "platform.h"
#include "platform.h"
#include "xbasic_types.h"
#include "xparameters.h"
Xuint32 *baseaddr_p = (Xuint32 *) XPAR_PS7_DDR_0_S_AXI_BASEADDR;

 
int main()
{
u32 A[2][2] = {4,3,7,9};
/**(baseaddr_p+0)=1;
*(baseaddr_p+1)=5;
xil_printf("baseaddr %d \n", *(baseaddr_p+0));
xil_printf("baseaddr %d \n", *(baseaddr_p+1));*/
int i=0;
int j=0;
int k=0;
xil_printf("start arm0 \n");
for (i=0; i<2; i++)
{
for (j=0; j<2;j++)
{
//write to the address
*(baseaddr_p+k)=(int)(A[i][j]);
k++;
}
}
xil_printf("end write ARM0 \n");
return 0;
}

 

 

Project ARM1: it will read the data written by ARM0 from the same DDR memory location :

 

#include <stdio.h>
#include "platform.h"
#include "platform.h"
#include "xbasic_types.h"
#include "xparameters.h"
 

Xuint32 *baseaddr_p = (Xuint32 *) XPAR_PS7_DDR_0_S_AXI_BASEADDR;

 
int main()
{

xil_printf("start ARM1 \n");
int k;
k=0;

for (k=0; k<4; k++)
{

xil_printf("baseaddr %d \n", *(baseaddr_p+k));
}
xil_printf("end write ARM1 \n");
return 0;
}

 

 

for the first project (ARM0): the writing into the basedaddr of DDR is done successfully, but my problem is when I run the second project of ARM1, I obtain always wrong results. 

 

 

Can you tell me if my process for executing two different projects sharing the DDR memory on both CPU0 and CPU1 is correct or not? Or the only solution is using the bootable solution which is indicated in the XAPP 1079?

 

Thanks in advance.

 

 

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Scholar trenz-al
Scholar
12,770 Views
Registered: ‎11-09-2013

Re: Communication between the 2 ARM Cortex A9?

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what problems you have?

 

you can just let both CPUs to run, and use say last block of OCM at 0xFFFF0000 for "mailbox" then you do not need worry about caches or anything

 

you can boot from sd-spi pr you can start it from debugger as well

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Adventurer
Adventurer
12,766 Views
Registered: ‎12-26-2013

Re: Communication between the 2 ARM Cortex A9?

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In my work, I used the debugger (without booting from sd-spi).

For the first project (ARM0), I debug its own software application and i have verified that the data are written very well in the baseadrr "0x00100000".

 

My problem is when I debug the second project after the first one, In the terminal, I get always wrong results:

 

start ARM1
baseaddr -369098691
baseaddr -369098715
baseaddr -369098712
baseaddr -369098699
end write ARM1

 

The problem is the ARM1 does not return the correct data of the matrix u32 A[2][2] = {4,3,7,9} which is written by the ARM0 .

 

 

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Scholar trenz-al
Scholar
12,761 Views
Registered: ‎11-09-2013

Re: Communication between the 2 ARM Cortex A9?

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cache?

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Adventurer
Adventurer
12,757 Views
Registered: ‎12-26-2013

Re: Communication between the 2 ARM Cortex A9?

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What do you mean by "cache" can you explain more?

 

 

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Scholar trenz-al
Scholar
20,060 Views
Registered: ‎11-09-2013

Re: Communication between the 2 ARM Cortex A9?

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DDR memory is usually cached, are you sure that the data written by one CPU that goes to write cache

is instantly visible in the read cache of the other?

 

thats why I suggested using OCM at FFFF0000 for mailboxes

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Adventurer
Adventurer
12,725 Views
Registered: ‎12-26-2013

Re: Communication between the 2 ARM Cortex A9?

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Thank you very much for your help.

It works perfectly now!

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Visitor gerald1010
Visitor
5,564 Views
Registered: ‎02-13-2015

Re: Communication between the 2 ARM Cortex A9?

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Hi makni,

 

can you post your solution? please include the source for ARM0 and ARM1!

 

Thanks,

G

 

 

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Visitor anil122
Visitor
1,605 Views
Registered: ‎02-27-2018

Re: Communication between the 2 ARM Cortex A9?

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can you tell how did you use the 2nd arm core because i created a separate project selecting ps_cortex_a9_1 and worte print statement but it is unable to print. Don't know what is the problem.Is there any setting i am missing out,,,,please help me out!
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