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Adventurer
Adventurer
618 Views
Registered: ‎11-19-2010

Configure PS for DDR3

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when configuring the DDR3 for a Zynq Processor, do I need to provide board physical information as below? (from a ps7.tcl file)

Are they essential? critical? It looks to me like trace length and delays are kind of redundant, are both necessary?

Is there a way to find or estimate them without board details?

 

CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {0} \
	CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {0} \
	CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM {0} \
	CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM {0} \
	CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM {0} \
	CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM {0} \
	CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM {0} \
	CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM {0} \
	CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {0} \
	CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM {0} \
	CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM {0} \
	CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM {0} \
	CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \
	CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \
	CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} \
	CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.229} \
	CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.250} \
	CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.121} \
	CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.146} \
	CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.271} \
	CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.259} \
	CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.219} \
	CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.207} \
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Moderator
Moderator
589 Views
Registered: ‎04-17-2011

Re: Configure PS for DDR3

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@jcabelYou need to provide correct trace lengths to be able to allow the PS DDR DRAM interface timing to be calibrated properly.

Refer to the Xilinx Answer Record: https://www.xilinx.com/support/answers/46778.html which has more details to help you out.

Regards,
Debraj
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Moderator
Moderator
590 Views
Registered: ‎04-17-2011

Re: Configure PS for DDR3

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@jcabelYou need to provide correct trace lengths to be able to allow the PS DDR DRAM interface timing to be calibrated properly.

Refer to the Xilinx Answer Record: https://www.xilinx.com/support/answers/46778.html which has more details to help you out.

Regards,
Debraj
----------------------------------------------------------------------------------------------
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Give Kudos to a post which you think is helpful and reply oriented.
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