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Adventurer
Adventurer
6,959 Views
Registered: ‎05-23-2010

Configuring PHY chip

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Hello all,

 

I am using Spartan 6 with DP83848I PHY chip on a custom board with ISE 12.4. I have EMACLite instantiated in my system.  The peripheral test of the EMACLite in interrupt and polling mode passes. When I connect the PC to the PHY through cable and FPGA is not yet configured, I can see a link established. When I configure the FPGA with the bit file, the link with PC is lost.

 

Configuring the PHY in 100 Mbps Duplex mode or Autonegotiation mode does not have any effect. Has anybody worked on DP83848I PHY chip and has experience configuring it? Please help me.

 

 

Regards,

 

wg

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Professor
Professor
8,931 Views
Registered: ‎08-14-2007

Re: Configuring PHY chip

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The fact that you establish a link when the FPGA is not loaded implies that

the strapping resistors are set for a working configuration.  You could work

backwards from the strapping settings (If you don't have actual resistors

on the board check the PHY data sheet for its internal pull up/downs) to

find a working register configuration.

 

Some things to look at:

 

Does the FPGA assert the reset signal to the PHY when it starts up?  This could

cause the PHY to re-read the strapping resistors.  If the FPGA actively drives any

of the strapping inputs (I think these are shared with LED functions on this PHY)

then you can change the PHY settings even if you don't issue any commands on

the MDIO interface.

 

What commands are you sending over MDIO when the FPGA starts up?  Does

removing these (disabling the MDIO interface) get you back to a working link?

 

 

-- Gabor

-- Gabor

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Professor
Professor
8,932 Views
Registered: ‎08-14-2007

Re: Configuring PHY chip

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The fact that you establish a link when the FPGA is not loaded implies that

the strapping resistors are set for a working configuration.  You could work

backwards from the strapping settings (If you don't have actual resistors

on the board check the PHY data sheet for its internal pull up/downs) to

find a working register configuration.

 

Some things to look at:

 

Does the FPGA assert the reset signal to the PHY when it starts up?  This could

cause the PHY to re-read the strapping resistors.  If the FPGA actively drives any

of the strapping inputs (I think these are shared with LED functions on this PHY)

then you can change the PHY settings even if you don't issue any commands on

the MDIO interface.

 

What commands are you sending over MDIO when the FPGA starts up?  Does

removing these (disabling the MDIO interface) get you back to a working link?

 

 

-- Gabor

-- Gabor

View solution in original post

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Adventurer
Adventurer
6,924 Views
Registered: ‎05-23-2010

Re: Configuring PHY chip

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Hello Gabor,

 

Thanks for your reply. You were right; the FPGA pins were changing the strapping configuration.  I changed the “Unused FPGA pins” option in ISE from Pull Down to Float and got back the link.

 

I have added the lwIP echo server reference example. I can see that there is a link now, but even after putting the PHY in Auto-negotiating or in 100 Mbps Duplex modes, there is no response to ping. I can see from Wireshark that the PC is sending the ARP packets but there is no response from FPGA. I would appreciate some pointers from you in this regard.

 

 

Regards,

 

wg

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Professor
Professor
6,918 Views
Registered: ‎08-14-2007

Re: Configuring PHY chip

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I haven't used LwIP myself, but I would have expected WireShark to see something from

the FPGA when you start it up, perhaps a "Gratuitous ARP".  So the first thing I would

check is if your transmit path is really working.  Checking the receive path could be

as simple as adding an LED signal that toggles when a packet is received.  You

need to be sure you're getting the ARP packets fom the PC.  Checking the transmit

path may be a bit trickier, but the PHY has LED outputs that should indicate transmit

activity if they are configured correctly.

 

-- Gabor

-- Gabor
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Adventurer
Adventurer
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Registered: ‎05-23-2010

Re: Configuring PHY chip

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Hello Gabor,

 

There was a resistor which was missing on LED_ACT pin. Adding a LED + resistor combination helped. Otherwise the Link_LED signal was high even when there was no link. Now the problem is that the Speed_LED pin and Speed bit in PHY status register shows a speed of 10 Mbps, but the Speed bit in the control register and PC shows a speed of 100 Mbps. And I am still not getting any response to ping. Also for some reason, when LEDs are configured in Mode 1, the LED keeps blinking even when I am not sending any packets from PC side.

 

 

Regards,

 

wg

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Adventurer
Adventurer
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Registered: ‎05-23-2010

Re: Configuring PHY chip

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Hello Gabor,

 

Now, I can see the gratuitous ARP from FPGA on the PC on Wireshark.  Still I get no response to ping.

 

 

Regards,

 

wg

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Adventurer
Adventurer
6,815 Views
Registered: ‎05-23-2010

Re: Configuring PHY chip

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Hello Gabor,

 

Finally the Ethernet connection is working. The interrupt mask used in the standard lwip Echo server example in 12.4 is XPAR_ETHERNET_MAC_IP2INTC_IRPT_MASK which is not really defined anywhere in xparameters.h. I replaced this with Emaclite interrupt mask and it worked. It's strange that the reference example would have a wrong interrupt mask which neither works for EmacLite nor TEMAC. But at least the system works now.

 

Regards

 

wg

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Professor
Professor
6,808 Views
Registered: ‎08-14-2007

Re: Configuring PHY chip

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That's great that you got it running.  Sorry I wasn't much help outside of the physical

connection part.  As I said I haven't used lwip myself, but I do have some experience with

these PHY chips.  Thanks for posting your solution in case others run into the same problem.

 

Regards,

Gabor

-- Gabor
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Newbie
Newbie
6,394 Views
Registered: ‎04-30-2012

Re: Configuring PHY chip

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thank you very much...

Your efforts really work for my custom board

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