UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Explorer
Explorer
5,268 Views
Registered: ‎11-17-2015

Control axi_interconnect:2.1 master to AXI Lite manually.

Jump to solution

Hi, 

 

I need to make one Master interface on the axi_interconnect to external because my block design contains Zynq but my top level instantiates my custom logic and the block design. The block design contains some AXI-Lite IPs from Xilinx. 

 

My custom logic needs an AXI Lite. However the axi_interconnect generates full AXI4 ports. I understand AXI Lite is a simpler than AXI4, and I dont want to risk a protocol disparities in my design. 

 

How can I control the protocol in the Master ports individually in 2015.4? I expanded the axi_interconnect but the Cross Bar doesnt allow me to Apply customizations. 

 

 

 

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Explorer
Explorer
10,297 Views
Registered: ‎11-17-2015

回复: Control axi_interconnect:2.1 master to AXI Lite manually.

Jump to solution
I guess I found a way out.

View solution in original post

0 Kudos
1 Reply
Highlighted
Explorer
Explorer
10,298 Views
Registered: ‎11-17-2015

回复: Control axi_interconnect:2.1 master to AXI Lite manually.

Jump to solution
I guess I found a way out.

View solution in original post

0 Kudos