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Contributor
Contributor
826 Views
Registered: ‎11-09-2007

Converting from AXI4 Interconnect to SmartConnect causes design to not fit

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I have a large design which I am targeting to a ZCU102 dev board that had been using AXI interconnect. I decided to change it to using SmartConnect and now the design fails to place due to lack of resources. Here's the message.

ERROR: [Place 30-487] The packing of instances into the device could not be obeyed. There are a total of 34260 CLBs in the device, of which 21815 CLBs are available, however, the unplaced instances require 22108 CLBs. Please analyze your design to determine if the number of LUTs, FFs, and/or control sets can be reduced.

Number of control sets and instances constrained to the design
Control sets: 11160
Luts: 287311 (combined) 343141 (total), available capacity: 274080
Flip flops: 322258, available capacity: 548160
NOTE: each CLB can only accommodate up to 4 unique control sets so FFs cannot be packed to fully fill every CLB

Prior to the change the design was at 66% utilization. 

One thing I am curious about is that I have multiple SmartConnect blocks in the design. This is the same with the AXI interconnect version. There are 80 or so IP blocks connected up and the block design is hierarchical so it is not practical to just use one giant smartconnect block. Vivado seemed to have no problem with this so I am assuming it's not a problem.

Does anyone have any suggestions as to what the problem might be? I thought SmartConnect was supposed to take less area.

Thanks,

-Pete

 

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Xilinx Employee
Xilinx Employee
756 Views
Registered: ‎10-04-2016

Re: Converting from AXI4 Interconnect to SmartConnect causes design to not fit

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Hi @sandbender,

We are still working on getting SmartConnect on par with AXI Interconnect for area/resource utilization. This effort is underway, but I can't commit to a release for completion.

For now, I recommend that you continue to use AXI Interconnect in your design. There are no plans to remove AXI Interconnect support for Zynq US+ or any of today's existing devices.

Regards,

Deanna

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5 Replies
Xilinx Employee
Xilinx Employee
757 Views
Registered: ‎10-04-2016

Re: Converting from AXI4 Interconnect to SmartConnect causes design to not fit

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Hi @sandbender,

We are still working on getting SmartConnect on par with AXI Interconnect for area/resource utilization. This effort is underway, but I can't commit to a release for completion.

For now, I recommend that you continue to use AXI Interconnect in your design. There are no plans to remove AXI Interconnect support for Zynq US+ or any of today's existing devices.

Regards,

Deanna

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Scholar ronnywebers
Scholar
716 Views
Registered: ‎10-10-2014

Re: Converting from AXI4 Interconnect to SmartConnect causes design to not fit

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@demarco I'm still trying ot figure out the main differences between both. Is SmartConnect meant to simplify things, to reduce area, to be faster, to use less resources? 

As long as both co-exist, how/on what base should we choose between the two? 

I remember with a Zynq design 2 years ago, I had an AXI interconnectx with +10 slave interfaces. Once I got to that +10, timing closure became impossible. Someone told me at that time that SmartConnect would solve that soon. But again, I'm still puzzled about the main differences between both....

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Xilinx Employee
Xilinx Employee
680 Views
Registered: ‎10-04-2016

Re: Converting from AXI4 Interconnect to SmartConnect causes design to not fit

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Hi @ronnywebers,

I apologize for the delayed response. I was out of the office for a few days.

SmartConnect has two important design goals: 1. it integrates more closely with Vivado to remove redundant logic and 2. it provides better performance scaling than AXI Interconnect. It handles the first by studying the meta-data from the AXI endpoint masters and slaves and optimizing out logic. For example, if none of the masters can generate narrow bursts, SmartConnect removes that logic.

With the second point, it should scale up to higher clock frequencies and support things like back-to-back single beat accesses.

The upgrade section of PG247 walks through scenarios where it is better to stay with AXI Interconnect versus upgrading to SmartConnect. As I mentioned before, the designers are still working on improving the area SmartConnect consumes compared to AXI Interconnect, particularly for AXI4-Lite endpoints.

https://www.xilinx.com/support/documentation/ip_documentation/smartconnect/v1_0/pg247-smartconnect.pdf#page=39

Regards,

Deanna

 

 

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Scholar ronnywebers
Scholar
661 Views
Registered: ‎10-10-2014

Re: Converting from AXI4 Interconnect to SmartConnect causes design to not fit

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no problem @demarco , thanks for the additional info!

I'm trying to understand the upgrading exceptions on page 39 in PG247...

1) If your design uses an AXI Data Width Converter, AXI Clock Converter, AXI Protocol Converter, AXI Data FIFO or AXI Register Slice core, and it is not directly connected to an interface of an AXI Interconnect v2 core, then continue to use it. Xilinx does not recommend using SmartConnect in a 1:1 configuration to perform those in-line functions at this time.

-> Q:  is an example of this a AXI4 Stream fifo that connects to the mm2s/s2mm ports of an AXI DMA? So one shouldn't insert a SmartConnect, is that what is meant with this paragraph?

 

 

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Xilinx Employee
Xilinx Employee
649 Views
Registered: ‎10-04-2016

Re: Converting from AXI4 Interconnect to SmartConnect causes design to not fit

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Hi @ronnywebers,

This statement does not apply to the AXI Stream FIFO. SmartConnect does not support the AXI4-Stream interface, so the traditional AXI4-Stream Interconnect and components are the correct IPs to use.

For reference, I am referring to the components in this PG:

https://www.xilinx.com/support/documentation/ip_documentation/axis_interconnect/v1_1/pg035_axis_interconnect.pdf

With traditional memory mapped AXI Interconnect, you had the option of instantiating a 1:1 AXI Interconnect that wrapped around a single component like a data width converter or a register slice OR you could just instantiate the data width converter or the register slice in the block diagram. What the statement from PG247 says is that if you are using a standalone AXI Data Width Converter, AXI Clock Converter, AXI Protocol Converter, AXI Data FIFO or AXI Register Slice, continue to do so. Do not upgrade to a 1:1 SmartConnect because it doesn't implement those single function IPs as efficiently at this time.

Regards,

Deanna

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