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Observer caccolillo
Observer
2,537 Views
Registered: ‎09-09-2010

Custom AXI IP block creation issues

Hi everybody,

I'm following this detailed tutorial on the creation processo of a custom peripheral on the AXI 4 lite bus:

 

http://www.fpgadeveloper.com/2014/08/creating-a-custom-ip-block-in-vivado.html

 

but the end result doesn't work as expected given the fact that the peripheral works as a bunch of register, as if after the synthesis, the peripheral doesn't embodies my custom logic, but rather the initial code generated by the peripheral wizard creator with the sole read/write registers.

Any hints about this issues on Vivado 2015.4 platform?

Thank you in advance.

Caccolillo. 

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3 Replies
Teacher muzaffer
Teacher
2,517 Views
Registered: ‎03-31-2012

Re: Custom AXI IP block creation issues

@caccolillo other than suggesting to follow the directions more carefully I don't have much. Instantiate the multiplier in the generated code before you package it.

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Xilinx Employee
Xilinx Employee
2,286 Views
Registered: ‎07-23-2012

Re: Custom AXI IP block creation issues

Can you please open the HDL files of the IP generated post changes and see if it has your logic? If not, you might have missed repackaging Ip or refreshing IP catalog post changes.
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Observer caccolillo
Observer
1,114 Views
Registered: ‎09-09-2010

Re: Custom AXI IP block creation issues

Following the directions in this tutorial:

 

https://www.youtube.com/watch?v=_F124UaZ-d0

 

I've been successful using Verilog.

I've then tried VHDL, incurring in this issue:

 

https://www.xilinx.com/support/answers/66322.html

 

but fixing the xparameters.h , everything works fine in VHDL too.

The process seems quite buggy in vhdl language.

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