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Participant twoism_
Participant
5,088 Views
Registered: ‎12-30-2015

DDR controller priority

Hello,
I need to prioritize the DevC requests to the DDR controller, with respect to AXI HP masters and the APU, to guarantee partial reconfiguration throughput. 

No other masters (e.g. PS DMA) are active in the system.


To do so I've tried to statically set the priority of the DDR controller's S1 port to an higher level:

REG_WRITE(AXI_PRIORITY_RD_PORT1, 0, 0xff);
REG_WRITE(AXI_PRIORITY_WR_PORT1, 0, 0xff);


And dynamically enabled urgent request on the same port:

 

REG_WRITE(SLCR_UNLOCK, 0, SLCR_UNLOCK_VAL);
REG_WRITE(DDR_URGENT, 0, 0x22);
REG_WRITE(SLCR_LOCK, 0, SLCR_LOCK_VAL);


However, those changes seem to have no effect and the reconfiguration throughput is still affected by other memory requests. What am I doing wrong? The software has been developed over FreeRTOS.

Thanks

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