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Observer adalaine
Observer
529 Views
Registered: ‎02-15-2019

DMA SG MM2S lantency

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Hello

I implemented DMA MM2S in SG Mode on a Ultrascale+.

The issue is that i am observing latency between descriptors when I use over 50 descriptors (approximately) : Tvalid is desasserted during 1 clock period before starting the next buffer (see photos below)

This latency is not observed between the first descriptors of the sequence ( approximately first 50 descriptors).

Did someone observe the same issue or have an idea about that ?

Thanks,

Antonin

Capture_Tvalid.png
Captur_Tvalid_zoom.png
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Xilinx Employee
Xilinx Employee
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Registered: ‎10-04-2016

Re: DMA SG MM2S lantency

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Hi @adalaine

If we looked at the Scatter-Gather channel, we might see some indication of what is contributing to the bubble. At best it would indicate that there is some contention in accessing DRAM.

AXI DMA doesn't guarantee that its streams are bubble-less. One option to smooth out bubbles is to add an AXI4-Stream Data FIFO in Packet Mode. It would store a streaming packet until the arrival of TLAST or the FIFO is full before pumping out data. Could you live with the latency this introduces?

Regards,

Deanna

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-04-2016

Re: DMA SG MM2S lantency

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Hi @adalaine,

I think we would need to see a trace of the M_AXI_MM2S interface to see whether those bubbles are coming from the read data side.

How many data transfers occur between the TVALID pulses? Does the number of data transfers align with the number of bytes to transfer per a descriptor?

I believe there is a typo in PG021 when it talks about the latency through AXI DMA. Table 2-2 says there are 6 clocks from "m_axi_mm2s_arvalid to m_axis_mm2s_tvalid." That should be 6 clocks from "m_axi_mm2s_RVALID to m_axis_mm2s_tvalid."

Regards,

Deanna

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Observer adalaine
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Registered: ‎02-15-2019

Re: DMA SG MM2S lantency

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Hi @demarco,

Here is a trace of the M_AXI_MM2S and M_AXIS_MM2S interfaces during a latency (Tvalid drop to zero during 1 clock cycle)

Some additionnal details about my test :

- I am using a Linux Kernel driver to configure the DMA IP

- The transfer is a serie of 100 descriptors, each descriptor point to a buffer containing 2048 bytes : 256 words of 64 bits

 

There is only one data transfer between two TVALID pulses, then the next pulse last for 256 data transfers : that matchs with the next buffer size.

I had a look in PG021, the 6 clocks delay from "m_axi_mm2s_RVALID to m_axis_mm2s_tvalid" seems conform as we can see on the trace.

Regards,

Antonin

Trace_Tvalid.png
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Xilinx Employee
Xilinx Employee
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Registered: ‎10-04-2016

Re: DMA SG MM2S lantency

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Hi @adalaine ,

From the trace you posted, it looks like the "bubble" on the AXI Stream interface where TVALID is deasserted is a result of AXI DMA needing to hold off the incoming read data on the memory mapped M_AXI_MM2S interface. You can see that spot where TREADY gets deasserted for a clock after the previous read burst completes. 

From a protocol standpoint, this is a valid thing for AXI DMA to do: if the read (aka transmit) channel needs to throttle the data bus, it is free to drop RREADY until it is ready to receive more read data. Why its internal state machines might need to do this is unclear.

A few idle clocks in an AXI Stream is generally not an issue for most designs, but there are exceptions. Is this the case in your design?

Regards,

Deanna

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Observer adalaine
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Registered: ‎02-15-2019

Re: DMA SG MM2S lantency

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Hi @demarco ,

Indeed, this "bubble" seems due to a latency from incoming read data on the memory mapped M_AXI_MM2S interface.

But I don't understand why these bubbles ocurs. I'm only working with the MM2S channel. Data are read from a buffer initialized by software before starting DMA transfer. I see no reason to throttle the data bus. Could it due to an internal issue of the DMA IP ? Did you already notice lantencies when working with this IP ?

The DMA IP is running at 100MHz.

Yes, this is the case in my design, I am using DMA IP to generate a signal, I could not have "bubbles" in the output data stream..

Regards,

Antonin

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Xilinx Employee
Xilinx Employee
297 Views
Registered: ‎10-04-2016

Re: DMA SG MM2S lantency

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Hi @adalaine

If we looked at the Scatter-Gather channel, we might see some indication of what is contributing to the bubble. At best it would indicate that there is some contention in accessing DRAM.

AXI DMA doesn't guarantee that its streams are bubble-less. One option to smooth out bubbles is to add an AXI4-Stream Data FIFO in Packet Mode. It would store a streaming packet until the arrival of TLAST or the FIFO is full before pumping out data. Could you live with the latency this introduces?

Regards,

Deanna

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Observer adalaine
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283 Views
Registered: ‎02-15-2019

Re: DMA SG MM2S lantency

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Hi @demarco 

Thanks for your answers.

I will look at the Scatter-Gather channel to see what happens.

That is what I am doing so far, using an AXI4-Stream Data FIFO. I wanted to know if I there was an another way without FIFO but it seems not. I will keep it.
Regards,

Antonin