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Observer guenselmann
Observer
390 Views
Registered: ‎12-03-2018

DMA and DataMover Unaligned Data Width Clarification

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Hi,

I need to transfer data packets of ~500 bytes size from PL-side DDR4 attached to a MIG into a custom AXI-Stream IP on Zynq US+. Currently I am using an AXI DataMover with DRE enabled because the (contiguous) data may start at any SDRAM address offset. This limits the TDATA width of the DataMover to 64 bits and results in too low throughput for my application.

Thus, I am exploring the option of using a DMA in Direct Register Mode (no scatter-gather) and setting the AXI-Lite control registers with my hardware block. PG021 states "optional Data Re-Alignment support for streaming data widths up to 512 bits". That would potentially speed things up significantly. However, the description of the programming sequence for Direct Register Mode in the same document on p. 71 says:

"For example, if Memory Map Data Width = 32, data is aligned if it is located at word offsets (32-bit offset ), that is 0x0, 0x4, 0x8, 0xC, and so forth. If DRE is enabled and Streaming Data Width < 128, then the Source Addresses can be of any byte offset."

Well, now I am confused. What is the maximum TDATA width of the DMA in Direct Register Mode? If it is indeed 128 bits I might have to get rid of the unaligned transfers altogether and fix the alignment myself with custom HDL, but having the DMA do it would be quite convenient.

Thanks in advance for any insight you might provide!

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Scholar jg_bds
Scholar
327 Views
Registered: ‎02-01-2013

Re: DMA and DataMover Unaligned Data Width Clarification

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I would expect proper operation. If you see otherwise, please add an update to this thread.

Think about what DRE is providing: you're adding a pipeline stage and a big shift matrix in front of the AXI-stream output. When the IP was originally created, a 64-bit stream along with an 8x8 matrix probably seemed like enough, so that became the top-end of the parameterized option. Or perhaps that's all that the logic in the older FPGA families could reasonably support.

Now with 10G and 40G interfaces (and more), 512- and 1024-bit AXI streams are more commonplace. And newer fabrics can support a 64x64 matrix.

-Joe G.

 

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Scholar jg_bds
Scholar
361 Views
Registered: ‎02-01-2013

Re: DMA and DataMover Unaligned Data Width Clarification

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The language of PG021 has been straining minds for years. See:

     https://forums.xilinx.com/t5/Design-Entry/AXI-DataMover-v5-1-Data-Realignment-Engine-DRE-with-8-bit-Stream/td-p/747704

You can bet that Xilinx is rarely criticized for releasing documentation ahead of new capabilities.

The supported AXI Stream widths allowed with DRE, have increased over the years--despite the version of the IP remaining at 7.1.

2019-09-12_18-56-33.jpg

Back in Vivado 2014.4, you can see that selecting an AXI Stream width of 128 or higher precluded the election of DRE:

2019-09-12_18-37-18.jpg

Yet in 2017.4 (and beyond), it's possible:

2019-09-12_18-40-12.jpg

Note the Help/Tip box in the current GUI is still quite old.

When you get that PG figured out, please explain it to the rest of us.

-Joe G.

 

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Observer guenselmann
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Registered: ‎12-03-2018

Re: DMA and DataMover Unaligned Data Width Clarification

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Thanks for your post :>

I hadn't looked at the changelog of the PG, so did not catch that. I guess we can conclude that the DMA should support unaligned transfers up to 512 bits TDATA width. Your post inspired me to check the Customization GUI for the DataMover again and indeed, Allow Unaligned Transfer can be ticked for TDATA widths up to 512 bits in Vivado 2018.3. Will this lead to undefined behaviour and is just not caught by the GUI?

Or, if one DMA channel is made of a DataMover and some additional control logic, why would the DataMover be limited to 64 bits anyway?

Clarification on this would be much appreciated!

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Scholar jg_bds
Scholar
328 Views
Registered: ‎02-01-2013

Re: DMA and DataMover Unaligned Data Width Clarification

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I would expect proper operation. If you see otherwise, please add an update to this thread.

Think about what DRE is providing: you're adding a pipeline stage and a big shift matrix in front of the AXI-stream output. When the IP was originally created, a 64-bit stream along with an 8x8 matrix probably seemed like enough, so that became the top-end of the parameterized option. Or perhaps that's all that the logic in the older FPGA families could reasonably support.

Now with 10G and 40G interfaces (and more), 512- and 1024-bit AXI streams are more commonplace. And newer fabrics can support a 64x64 matrix.

-Joe G.

 

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