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Observer
Observer
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Registered: ‎12-08-2017

Data Communication between PS and PL and PL and PS using the Master and slave ports in Zynq 7000, what should be the good AXI architecture?

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In a system of Zynq 7000(Zedboard). In the Zynq7 Vivado Block Design,

The following are the queries:

 

1. What should be the architecture for sending data from PS to PL and PL to PS? Is it essential to use an AXI peripheral like Stream Data FIFO, BRAM Controller? Can I make the M_AXI_GP0 and S_AXI_GP0 port as an external pin and write logic according to AXI4 Specifications? 

 

2.Coming to the SDK design of Zynq7, when the PL logic is compiled and .HDF is created, and when the blank project is created, when I refer to xparameters.h, I can only see the memory of the AXI peripherals like Stream Data FIFO, BRAM Controller if they are connected to the Slave or the Master ports, if these peripherals are not connected to the Slave and the Master Ports the memory map of the external pin of the M_AXI_GP0 and S_AXI_GP0 are vague, there is no actual detail of the registers in the AXI4 specification like Write Address, Write Data, Write Response, Read Address, Read Data channel signals. For example: awaddr, awburst, awcache, awid, awlen, awlock, awlock, awprot. Kindly elaborate how to read these values in PS if they are written in PL.

 

3. In a transaction between PS to PL, is writing data to the base address of the M_AXI_GP0 port or AXI-Peripheral sufficient to

transfer it to the PL? How will the valid signal generated from the PS side?

 

4. In a transaction between PL to PS, is reading data from the base address of the S_AXI_GP0 port or AXI-peripheral sufficient to read it in PS? How will the ready signal generated from the PS side?

 

5. If both M_AXI_GP0 and S_AXI_GP0  ports are used, I have found there will multiple conflicts in memory map in the address editor, what is the suitable memory map.

 

Thanks.

 

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Xilinx Employee
Xilinx Employee
3,751 Views
Registered: ‎10-04-2016

Re: Data Communication between PS and PL and PL and PS using the Master and slave ports in Zynq 7000, what should be the good AXI architecture?

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Hi @rembo,

There is a lot to unpack in your questions.

 

If you need to create a custom IP block that interacts with the PS, I recommend starting with UG1118. This walks through the Wizards that Xilinx provides to help you design an IP with AXI interface ports. It will be easier than designing an IP with this interface from scratch.

 

If you are just starting out with Zynq and IPI, I recommend packaging your IP such that it can be placed in the block diagram. This eliminates the need for external AXI ports and makes the hand off between hardware and software development easier. It is much easier to map your IP into the Zynq address space and manage the concerns you raise in question 2.

 

The best resource for understanding the AXI4 protocol is the specification from ARM. This explains what the various signals you list actually do.

https://silver.arm.com/download/download.tm?pv=1377613

 

For questions 3 and 4, you can only read/write to addresses that have an AXI slave mapped to that address. If an AXI Master tries to read/write an unimplemented address in Zynq-7000, it will hang.

 

I don't understand question 5. What are the conflicts you are referring to? 

 

Finally, if you haven't worked through a tutorial that takes you through a basic Zynq hardware design, exports it to SDK and gets some simple code running on the processor, I highly recommend it. I think that will help pull together some of the addressing questions you are asking. This one from FPGA Developer is a good place to start since it uses both PS master and slave ports:

http://www.fpgadeveloper.com/2014/08/using-the-axi-dma-in-vivado.html

 

Regards,

 

Deanna

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Xilinx Employee
Xilinx Employee
3,752 Views
Registered: ‎10-04-2016

Re: Data Communication between PS and PL and PL and PS using the Master and slave ports in Zynq 7000, what should be the good AXI architecture?

Jump to solution

Hi @rembo,

There is a lot to unpack in your questions.

 

If you need to create a custom IP block that interacts with the PS, I recommend starting with UG1118. This walks through the Wizards that Xilinx provides to help you design an IP with AXI interface ports. It will be easier than designing an IP with this interface from scratch.

 

If you are just starting out with Zynq and IPI, I recommend packaging your IP such that it can be placed in the block diagram. This eliminates the need for external AXI ports and makes the hand off between hardware and software development easier. It is much easier to map your IP into the Zynq address space and manage the concerns you raise in question 2.

 

The best resource for understanding the AXI4 protocol is the specification from ARM. This explains what the various signals you list actually do.

https://silver.arm.com/download/download.tm?pv=1377613

 

For questions 3 and 4, you can only read/write to addresses that have an AXI slave mapped to that address. If an AXI Master tries to read/write an unimplemented address in Zynq-7000, it will hang.

 

I don't understand question 5. What are the conflicts you are referring to? 

 

Finally, if you haven't worked through a tutorial that takes you through a basic Zynq hardware design, exports it to SDK and gets some simple code running on the processor, I highly recommend it. I think that will help pull together some of the addressing questions you are asking. This one from FPGA Developer is a good place to start since it uses both PS master and slave ports:

http://www.fpgadeveloper.com/2014/08/using-the-axi-dma-in-vivado.html

 

Regards,

 

Deanna

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