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2,781 Views
Registered: ‎05-04-2016

Debug two projects simultaneously on one machine using two JTAG USB cables

Hi

I'm using SDK 2017.1. What I'm trying to do is to debug two projects simultaneously on one machine using two JTAG USB cables.

 

Both are available like this:

forum1.png

 

When I burn .bit file I'm able to select different cables when "Autodetect" is uncheked:
forum2.png

After that I want to tell debugger which cable to use. To do that I go to Debug configurations - > Target setup - > Device select button.

But in this caseSDK doesn't provide this option for no reason:

forum3.png

 

 

Is there any other way to make debugger to work on speciefic cable

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8 Replies
Scholar pratham
Scholar
2,776 Views
Registered: ‎06-05-2013

Re: Debug two projects simultaneously on one machine using two JTAG USB cables

@leonid_galperinCheck this AR if it can be of any help
https://www.xilinx.com/support/answers/64252.html

-Pratham

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2,769 Views
Registered: ‎05-04-2016

Re: Debug two projects simultaneously on one machine using two JTAG USB cables

That's the point! In AR #64252 there is image that shows possibility to chose cable in debugger configuration dialog. The problem is that neither in SDK 2015.4 nor in 2017.1 there is no such option (See third picture on my post)

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Scholar pratham
Scholar
2,716 Views
Registered: ‎06-05-2013

Re: Debug two projects simultaneously on one machine using two JTAG USB cables

@leonid_galperin Looks like you have 2 targets. 501 and 601.

 

The 601 is where you are not able to find other device. From AR if you look, it's only one target local.

-Pratham

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2,711 Views
Registered: ‎05-04-2016

Re: Debug two projects simultaneously on one machine using two JTAG USB cables

You're absolutely right - I have two targets (or cables, it's the same).

The problem is that SDK recognize both when I want to program FPGA with .bit file and recognize only ONE when I want to debug software.
SDK show different information about same thing in two dialogs. Isn't it strange?

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Scholar pratham
Scholar
2,685 Views
Registered: ‎06-05-2013

Re: Debug two projects simultaneously on one machine using two JTAG USB cables

I have successfully debugged two projects in 2016.4. I don't have access to a board to test this out in 2017.1.
-Pratham

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2,662 Views
Registered: ‎05-04-2016

Re: Debug two projects simultaneously on one machine using two JTAG USB cables

Good for you.
But what should I do?
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2,660 Views
Registered: ‎05-04-2016

Re: Debug two projects simultaneously on one machine using two JTAG USB cables

I guess I found the difference between my situation and the one from AR above

 

 

forum4.png

 

 

 

 

I'm  using two Xilinx Platform USB II cables (like black box on the picture)
Apparently SDK has problem recognizing these two cables

 

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Xilinx Employee
Xilinx Employee
2,576 Views
Registered: ‎10-21-2010

Re: Debug two projects simultaneously on one machine using two JTAG USB cables

Hi,

The Device selection button in debug config should open the same dialog as the one in FPGA config. With 2017.1, I'm able to select the correct cable/device from debug config. Which OS/version are you using?

Until we figure out what the problem is, you may want to follow some manual steps. This could be a bit tedious, but is a one time effort and should help you move forward.

hw_server has a commandline option to debug targets only on a specific cable and ignore other cables and their targets. Below is an example.


xsdb% connect

xsdb% jtag ta ;# unfiltered targets
1 Digilent JTAG-SMT1 210203992034A
   2 xc7k325t (idcode 43651093 irlen 6 fpga)
3 Platform Cable USB 000015775a2c01
   4 system_ace_cf (idcode 0a001093 irlen 8)
   5 xc6slx45t (idcode 44028093 irlen 6 fpga)
xsdb% jtag ta -ta ;# get jtag target properties
{target_ctx jsn-JTAG-SMT1-210203992034A level 0 node_id 1 is_open 1 is_active 1 is_current 0 name {Digilent JTAG-SMT1 210203992034A} jtag_cable_name {Digilent JTAG-SMT1 210203992034A} state {} jtag_cable_manufacturer Digilent jtag_cable_product JTAG-SMT1 jtag_cable_serial 210203992034A}

{target_ctx jsn-JTAG-SMT1-210203992034A-43651093-0 level 1 node_id 2 is_open 1 is_active 1 is_current 0 name xc7k325t jtag_cable_name {Digilent JTAG-SMT1 210203992034A} state {} jtag_cable_manufacturer Digilent jtag_cable_product JTAG-SMT1 jtag_cable_serial 210203992034A idcode 43651093 irlen 6 is_fpga 1}

{target_ctx jsn-DLC9LP-000015775a2c01 level 0 node_id 3 is_open 1 is_active 1 is_current 0 name {Platform Cable USB 000015775a2c01} jtag_cable_name {Platform Cable USB 00015775a2c01} state {} jtag_cable_manufacturer Xilinx jtag_cable_product DLC9LP jtag_cable_serial 000015775a2c01}

{target_ctx jsn-DLC9LP-000015775a2c01-0a001093-0 level 1 node_id 4 is_open 1 is_active 1 is_current 0 name system_ace_cf jtag_cable_name {Platform Cable USB 000015775a2c01} state {} jtag_cable_manufacturer Xilinx jtag_cable_product DLC9LP jtag_cable_serial 000015775a2c01 idcode 0a001093 irlen 8}

{target_ctx jsn-DLC9LP-000015775a2c01-44028093-0 level 1 node_id 5 is_open 1 is_active 1 is_current 0 name xc6slx45t jtag_cable_name {Platform Cable USB 000015775a2c01} state {} jtag_cable_manufacturer Xilinx jtag_cable_product DLC9LP jtag_cable_serial 000015775a2c01 idcode 44028093 irlen 6 is_fpga 1}
xsdb% configp jtag-port-filter "Xilinx/DLC9LP/000015775a2c01" #; filter command to select a cable
xsdb% jtag ta ;# other cables are ignored as visible from this command
3 Platform Cable USB 000015775a2c01
   4 system_ace_cf (idcode 0a001093 irlen 8)
   5 xc6slx45t (idcode 44028093 irlen 6 fpga)
xsdb% ta
1 system_ace_cf
2 xc6slx45t
   3 MicroBlaze Debug Module at USER2
      4 MicroBlaze #0 (No clock)
xsdb% configp jtag-port-filter "Digilent/JTAG-SMT1/210203992034A" #; change the filter and see updated list
xsdb% ta
   5 xc7k325t
xsdb% jtag ta
1 Digilent JTAG-SMT1 210203992034A
   2 xc7k325t (idcode 43651093 irlen 6 fpga)
xsdb% configp jtag-port-filter "" #; remove the filter to see all the targets
xsdb% jtag ta
1 Digilent JTAG-SMT1 210203992034A
   2 xc7k325t (idcode 43651093 irlen 6 fpga)
3 Platform Cable USB 000015775a2c01
   4 system_ace_cf (idcode 0a001093 irlen 8)
   5 xc6slx45t (idcode 44028093 irlen 6 fpga)


In your case, you should launch two instances of hw_server on the machine where the cables are connected (use -s <port num> to start hw_server on a specific port), connect to each server from XSCT/XSDB and filter the targets (before filtering, get the target properties so that correct filter can be used). The filter string should be in the format “jtag_cable_manufacturer/jtag_cable_product/jtag_cable_serial”.

 

After this, you can create 2 target connections in SDK (one per the two instances of hw_server you have started, and in the program FPGA dialog/debug config, you can select the appropriate target connection to debug the correct cable/device 

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