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Observer apacker
Observer
854 Views
Registered: ‎01-19-2018

Design makes timing using FCLK_CLK0, but fails using FCLK_CLK1

Hello,

 

I am having a weird problem getting my design to make timing when I am using multiple FCLK's from the Zynq.  I have isolated it down to a much simpler design (block diagram snapshots attached).  All I have in this test design is an AXI UART connected to the GP0 port on the Zynq, through an AXI Interconnect, and the processor system reset IP.  All of this is clocked from FCLK_CLK0 on the PS, which is running at 100 MHz.  When I run implementation, this builds fine and makes timing.  However, if I switch to clocking it from FCLK_CLK1 on the PS, which is also running at 100 MHz, the design fails timing.  What am I doing wrong?

 

Thanks,

 

Asa

FCLK_CLK0.PNG
FCLK_CLK1.PNG
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3 Replies
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Scholar watari
Scholar
838 Views
Registered: ‎06-16-2013

Re: Design makes timing using FCLK_CLK0, but fails using FCLK_CLK1

Hi @apacker

 

Could you show me worst negative timing report, FCLK_CLK1 setting on Zynq IP ?

 

I suspect the following items.

 

- PLL type

- Location of some logic

- Jitter and/or uncertainty value (I guess they are suitable. But you need to improve it, if it is correct.)

 

Best regards,

Observer apacker
Observer
824 Views
Registered: ‎01-19-2018

Re: Design makes timing using FCLK_CLK0, but fails using FCLK_CLK1

Hi watari,

 

Thanks for your response.  I think I figured out how to fix my problem, although I don't fully understand what's going on.  While researching my problem, I came upon this Answer Record: https://www.xilinx.com/support/answers/65140.html

 

Inspired by that, I looked at the values of the CONFIG.PCW_FCLK_CLKx_BUF properties in my project, and they were not the same for CLK0 and CLK1:

 

get_property CONFIG.PCW_FCLK_CLK0_BUF [get_bd_cells ps]
TRUE

get_property CONFIG.PCW_FCLK_CLK1_BUF [get_bd_cells ps]
FALSE

I had not set these properties (I didn't even know they existed), so these must be the default values.  My vague understanding of this is that with these settings, FCLK_CLK1 is not configured for use as a "global" clock, so I think that must be why I was getting timing issues.

 

Once I did "set_property CONFIG.PCW_FCLK_CLK1_BUF TRUE [get_bd_cells ps]", my problems went away - the design worked fine using either FCLK_CLK0 or FCLK_CLK1.

 

Asa

Scholar watari
Scholar
781 Views
Registered: ‎06-16-2013

Re: Design makes timing using FCLK_CLK0, but fails using FCLK_CLK1

Hi @apacker

 

Generally, designer should use specified clock buffer on clock path.

If designer doesn't use it, clock path delay becomes worse.

 

In this case, because of you changed the property on PCW_FCLK_CLK1_BUF from false to true. Then, the result was fine.

 

Best regards,

 

 

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