05-05-2015 02:04 PM
I am using Div Gen 5.1 to generate a divider, i have found when an input is -ve and the other +pv it fails to give the correct result.
I am using this as part of a hardware design to be presented in a conference and need this issue resolved asap!
--I would also like to note, Xilinx software has been a constant battle to use (over the last 2 years!) with numerous bugs.
05-05-2015 02:46 PM
05-05-2015 10:37 PM
We don't have any known issue's which you have described.
Can you attach a simulation snapshot showing what you are seeing and what you are expecting to look at it and give you further suggestion on this.
05-06-2015 01:58 AM - edited 05-06-2015 03:47 AM
The I have worked out the issue is when the result is 0> x >-1 , i.e just negative fractionals quotient = 0, the quoitent part is not signed extended to a negative.
I guess then the question is how can I construct a reliable fixed-point result from the axi-result format Quotient-Frac, in the case that there is no quotient and I need to sign extend myself.
05-06-2015 02:10 AM