11-14-2007 05:02 AM
12-03-2007 10:37 AM
12-04-2007 02:43 AM
12-19-2007 02:39 PM
12-19-2007 10:19 PM
11-19-2008 09:50 PM
Did you get the PCI-e bridge design working ? I'm trying to do the same with ISE 10.1 SP3 on an XUPV5 (similar to ml505 but with a LX110T part) .
12-21-2008 12:23 PM
I have tried creating a project with the PCIe to PLB v3.0 core and a microblaze using the wizzard(using a fresh and updated install of EDK and ISE 10.1 and ). The design synthesizes correctly however when i try to use it i am incapable of reading or writing to the SRAM which is what should be accessed by default. I checked the configuration of the core and that is where the pcie to plb 1mb aperture is located.
another odd problem i noticed is some sort of configuration mishap where bar0 came up in PCItree but had a starting address of zero. however, when i cleaned out project files and re-implemented the project this problem disappeared.
the board i'm using is the ML506. i used the wizzard to generate a design for the ml505 and then changed the FPGA to the SXT version. the pinouts of the sx50t and the lx50t should be the same and the same PCB is used for the ml 506 and 505 boards. Does anyone know if this is ok? (i have gotten the core working in HDL without EDK).