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Observer larsge
Observer
11,683 Views
Registered: ‎09-12-2007

EDK 9.2i PLBv46 PCIE bridge ML505

Hi,
 
I am having problem with the PLB to Pcie Bridge.
 
I have built a system with the Base system builder for the ML505.
 
I only have a minimum of devices.
 
I can get all the devices on the ML505 board to function but not the Pcie bridge.
 
Is there some one else that have tried it?
 
The computer can see the board as a PCI memory controller but can not access any resources from the PCIE bridge.
 
Best regards
 
Lasse
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6 Replies
Advisor evgenis1
Advisor
11,617 Views
Registered: ‎12-03-2007

Re: EDK 9.2i PLBv46 PCIE bridge ML505

I had the same problem. I changed the class code from 05 (memory controller) to 0xFF.
Then you need to have a PCIe driver to talk to the device. I used Jungo evaluation.
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Observer larsge
Observer
11,606 Views
Registered: ‎09-12-2007

Re: EDK 9.2i PLBv46 PCIE bridge ML505

 
I can not get the pcie bridge to function.
 
Is it possible that you cand send me a working design for the ml505 board?
 
I would be very glad becuse i can not see any fault with my design.
 
Best regrads
Lasse Eriksson
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Xilinx Employee
Xilinx Employee
11,539 Views
Registered: ‎12-19-2007

Re: EDK 9.2i PLBv46 PCIE bridge ML505

Hi Lasse,

the following Answer record exists for this problem:

AR29780: http://www.xilinx.com/support/answers/29780.htm

Regards
Uwe



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Observer larsge
Observer
11,530 Views
Registered: ‎09-12-2007

Re: EDK 9.2i PLBv46 PCIE bridge ML505

Hi uweg,
 
Yes I know of this answer record but still no go.
 
If I copy PLBV46_PCIE ip core to my project "pcores" the CLK and RST appears in default connection to my CORE.
 
I have also check AR#24826.
 
I have no timing errors in my design.
 
I changed my cpu board then the design did not crash the OS but I can not write to the ML505.
 
If i run the PBLBV46_PCIE examples source i can not get any function values from the BRIDGE.
 
Best regards
Lasse
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7,334 Views
Registered: ‎11-04-2008

Re: EDK 9.2i PLBv46 PCIE bridge ML505

Hi larsge,

 

Did you get the PCI-e bridge design working ? I'm trying to do the same with ISE 10.1 SP3 on an XUPV5 (similar to ml505 but with a LX110T part) .

 

thanks

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Visitor kamiro87
Visitor
6,980 Views
Registered: ‎09-06-2008

Re: EDK 9.2i PLBv46 PCIE bridge ML505

I have tried creating a project with the PCIe to PLB v3.0 core and a microblaze using the wizzard(using a fresh and updated install of EDK  and ISE 10.1 and ).  The design synthesizes correctly however when i try to use it i am incapable of reading or writing to the SRAM which is what should be accessed by default. I checked the configuration of the core and that is where the pcie to plb 1mb aperture is located.

 

another odd problem i noticed is some sort of configuration mishap where bar0 came up in PCItree but had a starting address of zero.  however, when i cleaned out project files and re-implemented the project this problem disappeared.

 

the board i'm using is the ML506. i used the wizzard to generate a design for the ml505 and then changed the FPGA to the SXT version. the pinouts of the sx50t and the lx50t should be the same and the same PCB is used for the ml 506 and 505 boards. Does anyone know if this is ok?  (i have gotten the core working in HDL without EDK).

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