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Participant bmarechal
Participant
3,467 Views
Registered: ‎05-26-2011

EDK MIG DDR3 : map fails

Hello people !
 

I'm working on a SP605 board with EDK and SDK. I'm quite new to memory in general and to MIG in particular. However, I would need some DDR3 for an application so I went through the MIG workflow. I followed that guide: http://www.xilinx.com/support/documentation/boards_and_kits/sp605_MIG_pdf_xtp060_13.2.pdf
 

My system is a bit different however as I am using a MicroBlaze. So I used the axi_s6_ddrx_0_mcbx IP, as I got an... AXI bus. In the end, the windows are quite the same, just got some more options for AXI and an option to let EDK manage the DDR clock frequency (which decided it should be 400 MHz).
 

Then, I made the necessary connections, got some troubles with the ui_clk which I finally decided to plug on a 50 MHz clock. If you have any recommendation for me about this by the way, I would appreciate. And I tried to generate a bitstream. And there, map fails with error:

Pack:2501 - Symbol "MicroController_i/axi_s6_ddrx_0/axi_s6_ddrx_0/mcb_ui_top_0/mcb_raw_wrapper_inst/samc_0" of type MCB has a property "MEM_DDR3_WRT_RECOVERY" with an illegal value of "3".

 
I saw a post there mentionning a very similar issue. But I have not got the same value first; and second, I believe I got the right clock: 400 MHz... And I found no place where I could change that property.
 

Thank you for your support ! :smileywink:

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3 Replies
Xilinx Employee
Xilinx Employee
3,457 Views
Registered: ‎04-06-2010

Re: EDK MIG DDR3 : map fails

I recommend using Base System Builder to setup the memory controller. It should set up all of the clocks and constraints necessary for the controller to function on the SP605.
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Participant bmarechal
Participant
3,448 Views
Registered: ‎05-26-2011

Re: EDK MIG DDR3 : map fails

In my mind, the BSB is available only once, at initial stage. Is there anywhay to relaunch it on an existing design ?
 

The point is that I already have a design and as I'm a bit lazy, I would appreciate avoiding the process of redoing everything. Plus, I would like to understand what's exactly going on. With BSP, it will remain unknown to me.
I'll try BSB from the beginning anyway.

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Xilinx Employee
Xilinx Employee
3,435 Views
Registered: ‎04-06-2010

Re: EDK MIG DDR3 : map fails

You're correct that BSB is only available once. However, you can look at the MHS and look at how the Memory Controller is set up. Then you can make the modifications you need to do in the MHS.

The other thing worth trying is to clean all of your generated files and try rerunning through implementation. It's not a guarantee, but it could fix your issue.
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