02-07-2012 06:23 AM
Hello people !
I'm working on a SP605 board with EDK and SDK. I'm quite new to memory in general and to MIG in particular. However, I would need some DDR3 for an application so I went through the MIG workflow. I followed that guide: http://www.xilinx.com/support/documentation/boards_and_kits/sp605_MIG_pdf_xtp060_13.2.pdf
My system is a bit different however as I am using a MicroBlaze. So I used the axi_s6_ddrx_0_mcbx IP, as I got an... AXI bus. In the end, the windows are quite the same, just got some more options for AXI and an option to let EDK manage the DDR clock frequency (which decided it should be 400 MHz).
Then, I made the necessary connections, got some troubles with the ui_clk which I finally decided to plug on a 50 MHz clock. If you have any recommendation for me about this by the way, I would appreciate. And I tried to generate a bitstream. And there, map fails with error:
Pack:2501 - Symbol "MicroController_i/axi_s6_ddrx_0/axi_s6_ddrx_0/mcb_ui_top_0/mcb_raw_wrapper_inst/samc_0" of type MCB has a property "MEM_DDR3_WRT_RECOVERY" with an illegal value of "3".
I saw a post there mentionning a very similar issue. But I have not got the same value first; and second, I believe I got the right clock: 400 MHz... And I found no place where I could change that property.
Thank you for your support ! :smileywink:
02-07-2012 08:35 PM
02-08-2012 08:10 AM
In my mind, the BSB is available only once, at initial stage. Is there anywhay to relaunch it on an existing design ?
The point is that I already have a design and as I'm a bit lazy, I would appreciate avoiding the process of redoing everything. Plus, I would like to understand what's exactly going on. With BSP, it will remain unknown to me.
I'll try BSB from the beginning anyway.
02-14-2012 06:14 AM