UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Observer josephchau77
Observer
888 Views
Registered: ‎09-16-2018

Error when validate the Design

Hello

 

I following tutorial on the Xilinx doc UG1209 to create a block on the vivado 2018.2

after create the Zynq block and validate the design (i.e no further adding anyhting)

I got the following errors:

 

  • [BD 41-758] The following clock pins are not connected to a valid clock source:
  •       /zynq_ultra_ps_e_0/maxihpm0_fpd_aclk
  •       /zynq_ultra_ps_e_0/maxihpm1_fpd_aclk

 

How do I fixed these errors

 

Best Regards

Joe chau

0 Kudos
3 Replies
Moderator
Moderator
855 Views
Registered: ‎07-31-2012

Re: Error when validate the Design

Hi @josephchau77,

 

These two ports in PS are open and not being driven by clock source. Easy way is to connected them to pl_clk of PS to pass through.

 

Regards

Praveen


-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
Observer josephchau77
Observer
845 Views
Registered: ‎09-16-2018

Re: Error when validate the Design

Hello Praveen

 

Thanks for your response,

please admitted that I'm a newbies and learning curve 

Xilinx/Vivado/SDK Zynq UltraScale+ ZC102.

 

How do I connect the clock as you mention...?

 

Best Regards

Joe Chau

0 Kudos
Xilinx Employee
Xilinx Employee
837 Views
Registered: ‎08-15-2018

Re: Error when validate the Design

Hi @josephchau77,

As @pvenugo mentioned, the easiest way to do this is PS->PL clock passthrough. By default you should see pl_clk0, and can attach that to the AXI clock inputs like shown:

 

 

pl_clk.PNG

 

 

However in UG1209 we have you disable the AXI connections out of the Zynq IP block (page 18 step 7 -> page 19 step 10), so this shouldn't be necessary just yet :)

 

Hope that helps!

 

Thanks,

Clayton