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Observer
Observer
944 Views
Registered: ‎09-16-2018

Error when validate the Design

Hello

 

I following tutorial on the Xilinx doc UG1209 to create a block on the vivado 2018.2

after create the Zynq block and validate the design (i.e no further adding anyhting)

I got the following errors:

 

  • [BD 41-758] The following clock pins are not connected to a valid clock source:
  •       /zynq_ultra_ps_e_0/maxihpm0_fpd_aclk
  •       /zynq_ultra_ps_e_0/maxihpm1_fpd_aclk

 

How do I fixed these errors

 

Best Regards

Joe chau

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3 Replies
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Moderator
Moderator
911 Views
Registered: ‎07-31-2012

Re: Error when validate the Design

Hi @josephchau77,

 

These two ports in PS are open and not being driven by clock source. Easy way is to connected them to pl_clk of PS to pass through.

 

Regards

Praveen


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Observer
Observer
901 Views
Registered: ‎09-16-2018

Re: Error when validate the Design

Hello Praveen

 

Thanks for your response,

please admitted that I'm a newbies and learning curve 

Xilinx/Vivado/SDK Zynq UltraScale+ ZC102.

 

How do I connect the clock as you mention...?

 

Best Regards

Joe Chau

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Xilinx Employee
Xilinx Employee
893 Views
Registered: ‎08-15-2018

Re: Error when validate the Design

Hi @josephchau77,

As @pvenugo mentioned, the easiest way to do this is PS->PL clock passthrough. By default you should see pl_clk0, and can attach that to the AXI clock inputs like shown:

 

 

pl_clk.PNG

 

 

However in UG1209 we have you disable the AXI connections out of the Zynq IP block (page 18 step 7 -> page 19 step 10), so this shouldn't be necessary just yet :)

 

Hope that helps!

 

Thanks,

Clayton