09-20-2018 01:08 PM
I following tutorial on the Xilinx doc UG1209 to create a block on the vivado 2018.2
after create the Zynq block and validate the design (i.e no further adding anyhting)
I got the following errors:
How do I fixed these errors
09-24-2018 03:12 AM
These two ports in PS are open and not being driven by clock source. Easy way is to connected them to pl_clk of PS to pass through.
09-24-2018 05:58 AM
Thanks for your response,
please admitted that I'm a newbies and learning curve
Xilinx/Vivado/SDK Zynq UltraScale+ ZC102.
How do I connect the clock as you mention...?
09-24-2018 07:57 AM - edited 09-24-2018 08:07 AM
As @pvenugo mentioned, the easiest way to do this is PS->PL clock passthrough. By default you should see pl_clk0, and can attach that to the AXI clock inputs like shown:
However in UG1209 we have you disable the AXI connections out of the Zynq IP block (page 18 step 7 -> page 19 step 10), so this shouldn't be necessary just yet :)
Hope that helps!