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Observer bsutin
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Registered: ‎04-08-2009

Every 4th byte bad on 16-bit DDR2

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I am using mpmc for a 16-bit DDR2 single DRAM chip.  Every fourth byte reads back as 0x07, while the other three read and write as expected; ie, write 0x00000000, get 0x00000700, write 0xffffffff, get 0xffff07ff. The hardware runs fine under another core.   Any hints about where the problem could be?

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Observer bsutin
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Registered: ‎04-08-2009

Re: Every 4th byte bad on 16-bit DDR2

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Turns out that I was completely unaware of the MIG utility, which apparently generates the constraints needed for the timing. So I am assuming at this point that the timing is adequate for 3/4 of the bytes.

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Observer bsutin
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Registered: ‎04-08-2009

Re: Every 4th byte bad on 16-bit DDR2

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Turns out that I was completely unaware of the MIG utility, which apparently generates the constraints needed for the timing. So I am assuming at this point that the timing is adequate for 3/4 of the bytes.

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Visitor sunitakhilar
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Registered: ‎06-12-2012

Re: Every 4th byte bad on 16-bit DDR2

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Hi, I am new to FPGA with DDR interfacing. I am trying to send data to DDR2 thru Memory controller block Axi S6 DDRx MCB for Atlys board which is consisting of 1Gbit SDRAM(64M 16 Bits). Firstly I don't know whether the data is stored in DDR or not. How to check this as I don't know the address location of DDR where this data is stored. MCB configuration is set to ROW,BANK,Column where rows are 13bit and bank=3 (3bits) and column are 10bit. Please help... Many thanks in advance Sunita
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