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1,341 Views
Registered: ‎06-29-2015

Extra clock cycles in Zynq QSPI transfer causing errors

I am trying to read and write to a flash device using QSPI on Zynq device.

 

The number of clock cycles that I see on the SPI bus is not what I am expecting and I am out by one byte but do not understand why.

 

This is the sequence of what I am doing:

  1. Write 0x0000006B to TDX0 to start Fast read quad output at address 0.
  2. Write 0x00000000 to TXD0 for 4xbyte dummy writes to read.

 

What I expect is to see (48 clock cycles):

  1. 32x 1-bit write for command and address.
  2. 8x 1-bit write (switch over time to quad mode).
  3. 8x 4-bit transfer to read the 4 bytes.

 

But after step 2 I only see 6 cycles.  Why?

 

What may be related:

  1. How do I configure the Zynq to know if I am using 24-bit or 32-bit addresses after 0x6B command word, or is this not supported?
  2. How do I configure how many dummy bytes but be used between address and return data? I’ve changed LQSPI_CFG.DUMMY_BYTE but it does not have any effect.

 

Thanks,

 

Pieter

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6 Replies
Scholar ericv
Scholar
1,264 Views
Registered: ‎04-13-2015

Re: Extra clock cycles in Zynq QSPI transfer causing errors

Hi pieter.winter@stonethree.com

 

It sounds like you are using a single QSPI chip and not 2 in //.

Correct?

 

1 - Only 24 bit address is supported. For 32 bit addressing you have to set-up the QSPI extended address register.

2 - From what I've observed, the dummy byte(s) insertion is done using the width of the data transfer. In your case, if it's a single chip, each dummy byte corresponds to 2 dummy 4 bit read cycles. When it's 2 chips in //, each dummy byte becomes a single dummy cycle.

 

About 2 - because a few chips when set for max rate can only be programmed to use an odd number of dummy cycles, we've skipped trying to use the QSPI controller do deal with the dummy cycle insertion.

Instead our driver reads (with zero dummy cycles) the 1,2 or 4 bit data, and in S/W inserts them in a shift register skipping the equivalent number bits to match the number of dummy cycles before "recording" the real data.

 

 

 

 

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1,253 Views
Registered: ‎06-29-2015

Re: Extra clock cycles in Zynq QSPI transfer causing errors

Yes, I am only using a single QSPI chip.

 

I understand that it would be best if I added dummy cycles myself but it does look like the Zynq's QSPI peripheral is adding a dummy cycle, or something, and it does not make sense to me.  If I knew exactly what it was doing, then I could easily work around it.

 

I still do not understand why I see 6 cycles (in the dummy phase) where I expected 8.  If the single dummy cycle is done in quad mode, then it should be 2 cycles.

 

Is there any way that you can explain how the two writes to TXD0 result in 46 clock cycles?

 

 

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Scholar ericv
Scholar
1,239 Views
Registered: ‎04-13-2015

Re: Extra clock cycles in Zynq QSPI transfer causing errors

Hi pieter.winter@stonethree.com

 

Did you match the number of dummy cycles used by the QSPI controller with the value set in the QSPI chip?

The chip will output the data after the number it has been programmed with, no matter what the controller uses.

The QSPI controller dummies are only for skipping the non-data.

 

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1,234 Views
Registered: ‎06-29-2015

Re: Extra clock cycles in Zynq QSPI transfer causing errors

Hi Ericv,

 

No, my QSPI chip and controller does not match.  That is my problem, and I do not understand why.

 

Writing to TXD0 will always transfer 4 bytes.  I am writing to TXD0 twice, so it must be 8 bytes.  It is a QSPI write, so the controller should interpret the command, insert a dummy cycle, and switch to QSPI mode after that.  If this was the case, then I would see:

1.  1-byte command = 8 cycles.

2.  3-byte address = 24 cycles.

3.  1-byte dummy = 8 cycles in SPI mode, 2 cycles in QSPI mode.

4.  4-byte data in QSPI mode = 8 cycles.

 

I am not sure about what the controller does in step 3.  The datasheet is not clear, but as far as I can tell it can be one of:

a.  Do not insert a dummy cycle= 0 cycles.

b.  Insert a dummy byte in SPI mode = 8 cycles.

c.  Insert a dummy byte in QSPI mode = 2 cycles.

 

If I add the cycles from steps 1,2 and 4, then I get 40 cycles (do I already have it wrong at this point)?  Then, if I use the 3 possibilities from a, b and c, then I can get 40 cycles, 48 cycles or 42 cycles.  But I am getting 46.  Where am I going wrong?

 

Thanks for helping.

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Scholar ericv
Scholar
1,219 Views
Registered: ‎04-13-2015

Re: Extra clock cycles in Zynq QSPI transfer causing errors

The SPI clock is entirely controlled by the data in the TX FIFO.

Even when inserting dummy bytes, data from the TX FIFO is "pulled out"

 

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Participant 20801700
Participant
1,171 Views
Registered: ‎07-24-2017

Re: Extra clock cycles in Zynq QSPI transfer causing errors

Hi Pieter,

You can manually program the number of dummy cycles the QSPI uses during read operations by using 'register write'. Commonly QSPI flashes lets you program it both as non-volatile and as volatile. You may check your QSPI flashes datasheet and search for configuration registers.

 

-also check if the default value of dummy-cycles, may be it is actually 6.

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