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Registered: ‎06-21-2017

FIFO interfaces to GEM

I am working with the TX and RX FIFO interfaces from the GEM to the PL in a Zynq Ultrascale+, Vivado 2017.2, on Windows 7.  I noted some discrepancies from the Tech Ref Manual (UG-1085) and have a few questions. 

1) The Tech Ref Manual states that rx_w_data[31:0] is a 32 bit bus.  When I enable the GEM FIFO interface, it shows up on the Zynq Ultrascale+ block as emio_enet0_rx_w_data[7:0].

2) The Input and Output designations in Table 34-1 are either confusing or plain wrong.  For instance, the first entry:

Q1.png

This seems to indicate that the tx_r_sop signal is an input to the PL.  The block diagram plainly shows this as an input to the PS.  All signals seem to have the opposite direction from what is stated in the table.  It seems that the table is really written from the PS point of view but the heading on the second column would lead you to believe otherwise.

3) The transmit timing diagram does not match reality.  Figure 34-3 plainly shows the read signal toggling, one cycle active, one cycle idle as shown below:

Q2.png

 

What we are seeing is this signal active for a fairly long time (let's say 16 cycles), then idle for a while, then active in four clock bursts.  Can Xilinx supply a more representative timing diagram?

 

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Registered: ‎06-21-2017

Re: FIFO interfaces to GEM

Some more oddities with this interface.

We are receiving the discovery packets from wireshark.  We are getting four bytes of data, four bytes of zeros (missing four bytes of data).  This repeats until the end of packet.  The ILA sitting on the rx data is clocked from the rx clock which is running at 125MHz. 

The tx is similar.  We send data, but it is recieved by wireshark with four zero bytes interspersed with four good data bytes.  The state machine sending the data sends a runs on tx clock and sends a packet every 0.1 second.  The interface sends two packets before it stops responding.  Status shows no errors.

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Registered: ‎01-24-2018

Re: FIFO interfaces to GEM

Check the value of the network_config register (address 0xFF0E0004 for GEM3). You probably have bits 22:21 set to DMA mode instead of External FIFO mode. See attached screenshot.

 

 

Captura.PNG
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