08-13-2014 05:53 PM
I want to implement a fifo which has two axi slave interfaces. The reason I would like to have this implementation is so that the PCIe IP can write to the "inbound" fifo which can be read by the ARM A9 processor in Zynq. When the ARM is done processing the data, it can then write the data that it wants to communicate to the host on the "outbound" fifo for the PCIe driver to read.
I have gone through all the IPs in the IP catalog and it doesn't seem like there is anything for this purpose. Please propose a solution.
08-14-2014 06:31 AM
The way to connect AXI to a FIFO is using AXI-Stream FIFO, the makes AXIS streams in and out, it is simple to connect a AXIS to a native FIFO. Not sure you will get the through put you want tho.
08-14-2014 09:08 AM
Thanks for your reply.
If I am understanding what you're referring to, use a AXI Data Stream FIFO? However, that I can connect it to the PCIe for the data to flow in. How will I get the ARM to read the data from the FIFO? I was looking for a solution that will require me to drop in a fifo which has two slave ports and those two slaves can be just connected to the pcie and the ARM.
For your other proposed solution, I am assuming you meant that I can create an IP using the "Create AXI peripheral" options from the Tools. Is that right? I will have to implement glue logic to be able to interface the AXI data/addr along with the control signals to be able to store the data in the fifo. Is that right? Xilinx must have provided a fifo that performs read and write for two different masters. I am just not sure which IP is it. Please help!
08-15-2014 02:21 PM