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Explorer
Explorer
8,916 Views
Registered: ‎01-18-2014

FIR compiler and PS

Hi..

 

I have started an implementation of FIR filter using the FIR compiler block. The inputs to the core are provided by the PS. So, inorder to make connections between both i have used an AXI stream FIFO. 

So, intially i have tried an example program for the fifo which i got from the .mss file.

 

I have used the 'xllfifo_interrupt_example.c' program. Whenever i change the value written to the source address from '0' to '1', the interrupt test fails.

 

What would be the cause for this?

 

Thanks,

Gayathri

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31 Replies
Explorer
Explorer
8,892 Views
Registered: ‎01-18-2014

Re: FIR compiler and PS

Untitled.pngThe diagram below shows my connection..

Is this correctly made??

 

Also, instead of using interrupt i am using the polling mode for the fifo..

 

 

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Explorer
Explorer
8,881 Views
Registered: ‎01-18-2014

Re: FIR compiler and PS

console.pngi am using the example program  'XLlFifo_polling_example.c' with the above shown block diagram.

 

I have tried printing out the data which is passed to the source address. The values are printed as expected.

But, after it starts receiving the data, 'Xilinx FSBL' is printed and i had to power cycle my board. [as shown in the diagram]

 

I haven't changed anything of the example code.

 

What would be the cause of this??

Can anybody help me??

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Explorer
Explorer
8,823 Views
Registered: ‎01-18-2014

Re: FIR compiler and PS

why isn't there anybody to help??

Please provide me any suggestions..
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Explorer
Explorer
8,796 Views
Registered: ‎01-18-2014

Re: FIR compiler and PS

Can anybody help me in implementing an FIR filter in the PL logic and pass the datas from the PS??

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Explorer
Explorer
8,775 Views
Registered: ‎01-18-2014

Re: FIR compiler and PS

I have resolved this issue by modifying the linker script.

 

But, now, the problem is that the program is not returning to the main after reading data from the FIFO.

Also, the maximum packet size=11, number of packets=1.

 

The receive length in the code is obtained as some junk value =  536870923.

 

Do anyone know why this happens?

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Contributor
Contributor
8,754 Views
Registered: ‎03-11-2014

Re: FIR compiler and PS

Hi gayathri,

 

I don't have any solution for you problem, but I think this architecture is not the most suitable for what you want to do.

 

 

I would suggest a different architecture for you design. Instead of using the FIFO I would go for a DMA core that will read the data from the DDR3 through an AXI_HP port of the Zynq. Then the data as a stream will be sent to the FIR and after that through the DMA again and another AXI_HP port to return to another part of the DDR3 memory.

The data follow this path:

AXI_HP0 -> axi_mem_interconect -> axi_dma/M_AXI_MM2S -> axi_dma/M_AXIS_MM2S -> FIR/S_AXIS_DATA -> FIR/M_AXIS_DATA -> AXI_DMA/S_AXIS_S2MM -> AXI_DMA/M_AXI_S2MM -> AXI_mem_interconnect_1 -> S_AXI_HP2

 

The above diagram is not complete, as not all signals are connected. It is only as a demostration of what I suggest

 

I think this design is more efficient. It may look a bit more complicated.

 

If it does not suit your needs just ignore the post.

 

 

I hope this helps! Have fun :)

 

Nikos

Contributor
Contributor
8,750 Views
Registered: ‎03-11-2014

Re: FIR compiler and PS

The diagram disappeared!

 

I try again...

firDMA.JPG

firDMA.JPG
Explorer
Explorer
8,736 Views
Registered: ‎01-18-2014

Re: FIR compiler and PS

I hope that the dma connections to PS are via HP ports.

 

my design includes 2 fft implementations, and 2 different filters.

 

So, how will i be able to make all the connections through dma?

 

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Explorer
Explorer
8,725 Views
Registered: ‎01-18-2014

Re: FIR compiler and PS

hi nikos..

thank you for your suggestion..
i could make a working model of it
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Xilinx Employee
Xilinx Employee
8,869 Views
Registered: ‎08-01-2008

Re: FIR compiler and PS

http://japan.xilinx.com/support/documentation/sw_manuals_j/xilinx2014_3/ug898-vivado-embedded-design.pdf
Thanks and Regards
Balkrishan
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Explorer
Explorer
8,834 Views
Registered: ‎01-18-2014

Re: FIR compiler and PS

Now i am trying for implementing the filter with fractional coefficients (instead of integer type).

The input is also fractional type.

 

But, the output obtained is always zero..

 

The filter configuration is shown below..

fir.png

 

what would be the reason?

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Contributor
Contributor
8,818 Views
Registered: ‎03-11-2014

Re: FIR compiler and PS

How do you see the output?

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Explorer
Explorer
8,805 Views
Registered: ‎01-18-2014

Re: FIR compiler and PS

The results are seen in sdk.

 

I am reading the s2mm and mm2s buffer in sdk and displaying the results.

I have used simple dma transfer function.

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Contributor
Contributor
8,791 Views
Registered: ‎03-11-2014

Re: FIR compiler and PS

Do not forget about the processor's cache. When you are doing DMA transactions the processor does not know that the values stored in the memory have changed.

For example let's say the processor write the value 0x44 to address 0x00100000. Then the system in the PL reads this value (DMA through the HP port), does some calculations, and returns a new value (e.g 0x22) to the same address (again through the HP ports).

The processor does not know that the value has changed, so when it wants to read the value in address 0x00100000, it will look in the cache. This means that it will see the old value (0x44).

To prevent this from happening you should instruct the processor that this part of the cache is "dirty" by using the Xil_DCacheFlushRange() function.

The same happens when the processor writes the value to the memory. It will write it to the cache. The memory will most likelly not change, so you should use Xil_DCacheFlushRange.

 

A good way to see what exactly goes through the AXI HP ports is to add ILA debug cores monitoring the port. This way you will know if it the correct values are going to the DMA core and returned to the memory.

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Explorer
Explorer
8,786 Views
Registered: ‎01-18-2014

Re: FIR compiler and PS

Initially before the dma transfer starts the cache is flushed.

Also, this problem occurs only when i am trying to do fractional operations i.e., fractional coefficients, inputs and outputs instead of integer values.
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Teacher muzaffer
Teacher
8,763 Views
Registered: ‎03-31-2012

Re: FIR compiler and PS

is it possible that all your fractional values are less than 1 so they are truncated to 0 when you copy them to an integer buffer ?
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Explorer
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Registered: ‎01-18-2014

Re: FIR compiler and PS

what should be done??

 

beacuse almost all functions related to dma transfer are with integers only.

 

So, how would we process flosting point values??

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Teacher muzaffer
Teacher
8,743 Views
Registered: ‎03-31-2012

Re: FIR compiler and PS

You should give the FIR IP the bit pattern(s) it is expecting. If your FIR IP is (single precision) floating point, you should write bit pattern of a floating value into the buffer ie *(float*)&dma_buffer[0] = float_data[0]; ie just cast the pointer of the dma buffer into the format you need to write.

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Explorer
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Registered: ‎01-18-2014

Re: FIR compiler and PS

I wanted to write a fractional value to the "streaming to memory mapped buffer". But the function  XAxiDma_SimpleTransfer

takes in only u32 format for the buffer address. Does it cause any problem with the fractional values?. 

 

 

XAxiDma_SimpleTransfer(&axi_dma, (u32)s2mm_buf,filter_params*4, XAXIDMA_DEVICE_TO_DMA);

 

So, in this case, where will i be able to do a pointer typecasting?

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Teacher muzaffer
Teacher
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Registered: ‎03-31-2012

Re: FIR compiler and PS

s2mm_buf is the address of a block of memory. DMA transfer the contents of this block of memory. You do the casting while you fill this memory block. The dma function accepts a 32 bit value for the address, it is not even an address type as the actual type of the value in the buffer does not matter.
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Explorer
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Registered: ‎01-18-2014

Re: FIR compiler and PS

Initially i thought so and decalred the s2mm buffer as float* .

 

But, in that case, the values read from this buffer were always zero.

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Teacher muzaffer
Teacher
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Registered: ‎03-31-2012

Re: FIR compiler and PS

>> Initially i thought so and decalred the s2mm buffer as float* .
you mean:

float s2mm[BUF_SIZE];
s2mm[0] = 1.8;
s2mm[1] = 2.5; etc. ?
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Teacher muzaffer
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Registered: ‎03-31-2012

Re: FIR compiler and PS

in the code you sent all buffers are arrays of int. how do you write to stim_buf?
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Teacher muzaffer
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Registered: ‎03-31-2012

Re: FIR compiler and PS

>> instead of using int type for the result buffer and s2mm_buf, mm2s_buf, i have changed them to float*

this is where the problem is. those buffers should be of type float not float*
float stim_buf[BUFSIZE] = {1.5, 2.8, ...};

 

BTW, did you really make a floating point FIR? 

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Explorer
Explorer
8,343 Views
Registered: ‎01-18-2014

Re: FIR compiler and PS

I had tried for a filter with fractional coefficients..

Not floating point format...fixed point format..

 

 

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Teacher muzaffer
Teacher
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Registered: ‎03-31-2012

Re: FIR compiler and PS

the bottom line is you need to store the bit pattern the fir filter expects in the stim_buf memory area. If FIR expects fixed point data, declare it as int then scale your fractional values to the right value. Suppose your FIR needs 4.20 fixed point values, then you need to say
int stim_buf[];
stim_buf[0] = 2.85 * 1 << 20;
here you know 2 fits into 4 bits so you multiply everything by 2^20 to get the bit pattern of a 4.20 fixed point number which can be stored in an int.
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Explorer
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Registered: ‎01-18-2014

Re: FIR compiler and PS

So, in this case we have to scale our input so that it would be integers.

Also, the the output will also be in integer format and hence, at the end we will have to scale it down accordingly.

Is this the correct interpretation of what you meant??
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Teacher muzaffer
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Registered: ‎03-31-2012

Re: FIR compiler and PS

Yes.

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Explorer
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8,009 Views
Registered: ‎01-18-2014

Re: FIR compiler and PS

Can anybody help me in implementing a reloadable fir filter??

 

I have posted in http://forums.xilinx.com/t5/Digital-Signal-Processing-IP-and/Reloadable-filter-outputs-not-proper/m-p/554240

 

but, nobody has replied till now..

 

any help would be greatly appreciated..

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