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Anonymous
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FSBL errors when programming PL

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Hi All,

 

I created a bootable image in SDK using the bootgen application.

The bootable image contains (in the following order):

 

-FSBL was created using the template in SDK.
-bitstream: custom (basic) project that contains an XPS system and some custom firmware logic.
-second stage bootloader

 

Now when I created the FSBL in SDK I set the FSBL_DEBUG and FSBL_DEBUG_INFO compilation flags and when I look at my COM PORT, it prints this:

 

Xilinx First Stage Boot Loader
Release 14.3 Apr 30 2013-09:34:36
Silicon Version 1.0
Boot mode is SD
Bitstream Download Start
...................................................................................................
...................................................................................................
Xilinx First Stage Boot Loader
Release 14.3 Apr 30 2013-09:34:36
Silicon Version 1.0
WDT_RESET_OCCURED
Boot mode is SD
Bitstream Download Start
...................................................................................................
...................................................................................................

And it just keeps printing that second part with the WDT_RESET_OCCURED.

 

Does anyone have any ideas what could be causing this?

 

Thanks so much in advance.

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Anonymous
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Re: FSBL errors when programming PL

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I have actually gotten my issue resolved. Just an FYI to anyone else who could have this issue, the StartupClk:JtagClk option is what caused my issue.

View solution in original post

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Anonymous
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Re: FSBL errors when programming PL

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I forgot to add that I left offset, alignment and allocation parameters blank when I generated the bootable image.

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Scholar
Scholar
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Registered: ‎02-27-2008

Re: FSBL errors when programming PL

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WDT == Watch Dog Timer

 

You have created a watchdog timer, and you are not kicking (tickling, strobing) it, so it is timing out.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Anonymous
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Re: FSBL errors when programming PL

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But if nothing else is up and running (since it's still in the FSBL), what should be strobing/tickling the watchdog timer?

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Scholar
Scholar
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Registered: ‎02-27-2008

Re: FSBL errors when programming PL

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Now you know why it is complaining!

 

Go back, find where you turned on the WDT, and don't enable it.  When you have a better understanding of how everything works, then I would suggest you use the WDT, if you want to....

 

Start as simple as you possibly can  Starting with everything all at once is very likely to cause you to lose your mind.  Not because there is anything 'wrong' with anything, but because it gets far too complex, far too fast.

Austin Lesea
Principal Engineer
Xilinx San Jose
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Anonymous
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Re: FSBL errors when programming PL

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Hi Austin,

 

Thanks for your reply.

 

I figured out that my problem was that I used the predefined zc702_hw_platform in SDK when building my FSBL, which has the WDT defined, causing it to be initialized when the FSBL runs.

 

I fixed it by exporting my hardward from XPS (which has no WDT since I don't need it) and recreated by FSBL.


I got passed that issue but am now fighting another error.

 

From my debug output I get:

 

PCAP transfer timed out
 PCAP_FPGA_DONE_FAIL
BITSTREAM_DOWNLOAD_FAIL  FSBLStatus = 0xA005

 

(Entire log is attached)

 

Tracing through the FSBL, it looks as though it is timing out because it is waiting for the DONE signal from the PL.

 

I am beginning my in-depth review of my output log as well research into what could be causing this issue, but any insight is greatly appreciated.

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Scholar
Scholar
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Registered: ‎02-27-2008

Re: FSBL errors when programming PL

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d,

 

Zynq initializes witht the processor having full control of the FPGA configuration (PCAP belongs to the processor, and must be released for the FPGA to use ICAP, for example).  If there is not a valid bitstream as part of the FSBL, then it will fail to program (there needs to be at least a dummy, or valid blank bitsream to load so you can get to DONE goes high).

 

Was there a valid bitstream to add to the fsbl?

 

Another possibility is that the LOCKED signals on the MMCM's, DCI, etc. may be used to gate DONE going high,  Is there anything in your design that requires those signals?  If so, check the bitstream options and change them so DONE is not gated by those signals.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Anonymous
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Re: FSBL errors when programming PL

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Hi Austin,

 

Yes, I included a valid bistream when using bootgen.

 

Also

 

(1) In my design, I actually do not have any MMCM's instantiated in my design

 

(2) I am using the following bitgen command when generating my bitstream.

         bitgen -g StartupClk:JtagClk -intstyle ise -w my_test.ncd my_test_cs.bit my_test.pcf

     When you say, change them so DONE is not gated by those signals, do you mean the -LCK_cycle option?

 

 

 

 

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Anonymous
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Re: FSBL errors when programming PL

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If so, I believe the default option is NoWait.... but maybe I need to set the Match_cycle option... the UG says it defaults to Auto... should I set it to NoWait?

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Anonymous
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Re: FSBL errors when programming PL

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I actually just regenerated my bitstream with both options and it still times out.

 

bitgen -g StartupClk:JtagClk -g Match_cycle:NoWait -g LCK_cycle:NoWait -intstyle ise -w my_test.ncd my_test_cs.bit my_test.pcf

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Anonymous
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Re: FSBL errors when programming PL

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I have actually gotten my issue resolved. Just an FYI to anyone else who could have this issue, the StartupClk:JtagClk option is what caused my issue.

View solution in original post

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Registered: ‎01-22-2019

Re: FSBL errors when programming PL

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I have this problem with my target open in Vivado via JTAG. It bricks the FPGA bitsteram transfer. Simply closing the server solves the problem for me, there is nothing wrong with the boot per se.

 

vivado_hw_man.png
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