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Newbie yaniv_ch
Newbie
2,952 Views
Registered: ‎08-10-2010

FSL performance

Hi

I'm using microblaze(spartan6) with fsl connection to my fpga blocks.

 I don't have external memory on board.

 I need to read\write fsl with data blocks of 257*32bit.

my SW initialize array of 257*32bit blocks and send it to fsl.

in chipscope I see the the delay between 2 writes is 7 clocks.

 if I'm using blocks of 4*32bits the delay is 2 clocks and even 1 clk when C_AREA_OPTIMIZED is 0.

how can I minimize the 7 clocks delay to 1or 2 clocks?

do i need data cache except  DLMB?

thanks

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Explorer
Explorer
2,940 Views
Registered: ‎07-08-2008

Re: FSL performance

Hi,

 

You are using microblaze, which initializes the array from software.

Your software (binaries) are placed in BRAMs (?) since you are saying that you don't use external memory.

What about caches - you don't write anything about them.

 

The problem probably occurs because you have to remember that you need to fetch instructions (the ones responsible for the FSL communication) from the memory (BRAMs) as well as data.

Your performance observed in chipscope depends on communication between Microblaze and that memory.

 

BRAM are very fast in comparison to external memory so this is a way to go for you.

 

The problem with 257 (> 1k) large chunk of block occurs since it probably does not fit into the cache in contrast to the 4 large chunk.

In such case you have cache miss and this couses the penalties which you see in a chipscope.

 

Greetings, Mariusz.

 

--
Mariusz Grad.
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