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Adventurer
Adventurer
274 Views
Registered: ‎06-22-2018

Force Zynq-7's MIO pin output low before entering the user application

I connect the Zynq-7's several MIO pins (MIO9~MIO14) to external devices' function enable pins. The pin is active high. So I need maintain them low before my PS code taking control. I need know their state at two booting mode:

1. Booting from JTAG (that is when debugging via JTAG).

2. Booting from QSPI.

If they all are tri-state, then external pull-downs will solve my problem. But if they are pulled up, then I need to know the pull-up value, and choose proper external pull-down resistor value to override the internal pull-ups. 

I have no clues for now, any help?

Thanks.

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Xilinx Employee
Xilinx Employee
236 Views
Registered: ‎10-30-2017

Re: Force Zynq-7's MIO pin output low before entering the user application

Hi @diverger,

 

Please refer this AR#56787 (https://www.xilinx.com/support/answers/56787.html) this AR helps you to understand the default state of the MIO pins.

Best Regards,
Srikanth
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