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Visitor xmouseii
Visitor
3,420 Views
Registered: ‎12-27-2016

How can I simulate a zynq with PS & PL?

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How can I simulate a zynq with PS & PL? I using Planahead 14.6

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Teacher muzaffer
Teacher
5,906 Views
Registered: ‎03-31-2012

Re: How can I simulate a zynq with PS & PL?

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@xmouseii alas there is no easy way to simulate PS & PL together. Right now the best thing you can do is to use what's called the "Zynq BFM" which is basically a set of AXI models which allows you to generate transactions just at the axi connectivity between PS & PL but this doesn't allow you to run any code on the processor, you have to convert your processor transactions manually to axi transactions.

 

There are qemu models of zynq which allow you to simulate & debug your code and it's theoretically possible to integrate qemu and an rtl simulator through DPI. Xilinx has suggested that they might implement something like this for 2017.1. We will see if they actually can pull it off.

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2012

Re: How can I simulate a zynq with PS & PL?

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Please refer below link documents  and check whether you can find useful information related your query

https://www.xilinx.com/support/documentation/application_notes/xapp744-HIL-Zynq-7000.pdf

https://www.xilinx.com/support/documentation/application_notes/xapp1086-secure-single-fpga-using-7s-idf.pdf

 

 

Also refer https://www.xilinx.com/support/answers/61846.html. This answer record was wrote with respect to Vivado  tools users. In  case if you have Vivado tools and if you wish to try example project then it is useful. 

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Teacher muzaffer
Teacher
5,907 Views
Registered: ‎03-31-2012

Re: How can I simulate a zynq with PS & PL?

Jump to solution

@xmouseii alas there is no easy way to simulate PS & PL together. Right now the best thing you can do is to use what's called the "Zynq BFM" which is basically a set of AXI models which allows you to generate transactions just at the axi connectivity between PS & PL but this doesn't allow you to run any code on the processor, you have to convert your processor transactions manually to axi transactions.

 

There are qemu models of zynq which allow you to simulate & debug your code and it's theoretically possible to integrate qemu and an rtl simulator through DPI. Xilinx has suggested that they might implement something like this for 2017.1. We will see if they actually can pull it off.

- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
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