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Visitor paradoxfx
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Registered: ‎12-09-2013

How can PL use clock from PS

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I've already configured PS to make it output FCLK_CLK0 to PL. The HDL code is already written in PL (IP core not used). The question is how to use FCLK_CLK0 clock in PL? It's not a FPGA pin, and I can't find the signal.
Besides, I've created the Wrapper.v for the ARM PS. But it seems this file can't be modified. So how can the Wrapper.v work together with my hand written HDL code?
Thank you.

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Teacher muzaffer
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Registered: ‎03-31-2012

Re: How can PL use clock from PS

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You need to instantiate the PS module in your top level RTL file. Top level or chip level design includes the PS and anything you need to define in PL. The FCLK_CLK0 signal is an output from PS so you can define a wire at top level, connect it to PS output and use it or you can define a PL top, instantiate PS and PL top at the chip top level and make FCLK_CLK0 an input to PL top and go from there.
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Teacher muzaffer
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Registered: ‎03-31-2012

Re: How can PL use clock from PS

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You need to instantiate the PS module in your top level RTL file. Top level or chip level design includes the PS and anything you need to define in PL. The FCLK_CLK0 signal is an output from PS so you can define a wire at top level, connect it to PS output and use it or you can define a PL top, instantiate PS and PL top at the chip top level and make FCLK_CLK0 an input to PL top and go from there.
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Xilinx Employee
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Registered: ‎06-14-2012

Re: How can PL use clock from PS

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Please check the following design. It uses the FCLK0 for BRAM in the PL.

http://www.xilinx.com/support/answers/47266.html

 

Hope this helps.

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Visitor paradoxfx
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Registered: ‎12-09-2013

Re: How can PL use clock from PS

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 Thanks for your reply. Could the top level RTL be a HDL file, then I instantiate the PS-wrapper.v and other hand-written HDL  from the top HDL?

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Visitor paradoxfx
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Registered: ‎12-09-2013

Re: How can PL use clock from PS

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Thanks for your reply. I'm using Vivado and I can get the FCLK clock for the IPcores in PL by using the IP integrator. The question is the HDL is hand-written, so I could not use the same method to wire my block into PS block.

 

In other words, I'm using a low cost ZYNQ board called 'MicroZed'.  It only has one external clock for PS, not for PL, and I don't have the interface card, so I must introduce the clock from PS into PL. At present, the PL parts is very simple, it only need an external clock and do not have other relation to PS...

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Teacher muzaffer
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Registered: ‎03-31-2012

Re: How can PL use clock from PS

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>> Could the top level RTL be a HDL file, then I instantiate the PS-wrapper.v and other hand-written HDL from the top HDL?

Yes, absolutely.

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Xilinx Employee
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Registered: ‎06-14-2012

Re: How can PL use clock from PS

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Yes you could

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Visitor paradoxfx
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Registered: ‎12-09-2013

Re: How can PL use clock from PS

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Thanks. I'll have a try.
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Registered: ‎08-09-2016

Re: How can PL use clock from PS

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Thank you for your effort.

But can you elaborate a bit more please.

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Visitor truptic91
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Registered: ‎04-18-2017

Re: How can PL use clock from PS

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Hi,

 

I am working on xc7z100ffg900 in Vivado 2016.4.

 

I want PS clock in PL.

 

I have instantiated ZYNQ7_processing _system block in my top module as you mentioned. In ZYNQ7_processing_system, other applications are also initialized along with PL clocks. By PS generated PL clock, I am driving a simple counter in my top module.

 

In synthesis, its not giving any error but its not locking pins of PS module. Whereas in system generated XDC, pins are mapped properly.

After implementation, I am getting critical warnings for each MIO pins.

Those are mainly:

 

[Netlist 29-160] Cannot set property 'iostandard', because the property does not exist for objects of type 'pin'. ["/zynqn/zynqn.srcs/sources_1/bd/PS_Block/ip/PS_Block_processing_system7_0_1/PS_Block_processing_system7_0_1.xdc":33]

 

[Netlist 29-160] Cannot set property 'PACKAGE_PIN', because the property does not exist for objects of type 'pin'. ["zynqn/zynqn.srcs/sources_1/bd/PS_Block/ip/PS_Block_processing_system7_0_1/PS_Block_processing_system7_0_1.xdc":34]

 

[Netlist 29-160] Cannot set property 'slew', because the property does not exist for objects of type 'pin'. ["/zynqn/zynqn.srcs/sources_1/bd/PS_Block/ip/PS_Block_processing_system7_0_1/PS_Block_processing_system7_0_1.xdc":35]

 

[Netlist 29-160] Cannot set property 'drive', because the property does not exist for objects of type 'pin'. ["/zynqn/zynqn.srcs/sources_1/bd/PS_Block/ip/PS_Block_processing_system7_0_1/PS_Block_processing_system7_0_1.xdc":36]


[Netlist 29-160] Cannot set property 'pullup', because the property does not exist for objects of type 'pin'. ["/zynqn/zynqn.srcs/sources_1/bd/PS_Block/ip/PS_Block_processing_system7_0_1/PS_Block_processing_system7_0_1.xdc":37]


[Netlist 29-160] Cannot set property 'PIO_DIRECTION', because the property does not exist for objects of type 'pin'. ["/zynqn/zynqn.srcs/sources_1/bd/PS_Block/ip/PS_Block_processing_system7_0_1/PS_Block_processing_system7_0_1.xdc":38]

 

The XDC pointed in warnings, is system generated.

 

How can I verify that whether my connections are correct or not? and why is it giving critical warnings when XDC is system generated?

 

 

I am attaching the screenshot of system generated XDC and critical warnings.

Thanking in advance.

 

Screenshot from 2017-04-21 19:39:07.png

 

 

Screenshot from 2017-04-21 19:40:09.png

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Teacher muzaffer
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Registered: ‎03-31-2012

Re: How can PL use clock from PS

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@truptic91You don't need any constraints for MIO pins at all. They are at fixed locations and their VCCIO levels are setup within PS7 configuration in Vivado and communicated over hdf file to FSBL. 

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Visitor truptic91
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Registered: ‎04-18-2017

Re: How can PL use clock from PS

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@muzaffer I am not constraining any MIO through xdc.

The screenshot which I have attached is system/tool generated xdc. I didn't write it.

 

But while making build,  its giving critical warning and I can't see that pin is locked.

For eg. I am using UART from MIO. The pin mapping for it, is-

RX- Package pin: A20- MIO38

TX- Package pin: F18- MIO39

but I cannot see that those pins are locked.

whereas package pin F15 is locked with some signals in top module. There is -- in symbol.

on the other hand UART Rx pin- A20 is unmapped. you can see it screenshots below.

 

My question is how to verify pin mapping for MIO when its not shown in synthesis/implementation?

 

Thanks

 

pin_mapping1.png

 

pin_mapping2.png

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