01-22-2020 04:36 AM
I am testing the functionality of DMA IP. I am more interested in Scatter Gather method.
I had created the Block design using ZCU102 board.
After creating the design how to test the DMA fuctionality on software?
I want check the data flow from DMA->DDR and DDR->DMA
How I can achieve this?
Please help me.
I will attach the .tcl script of my project.
01-24-2020 10:45 AM - edited 01-24-2020 10:53 AM
For learning/testing purposes, I would:
1. Use the R5 for starters.
2. Enable packet mode on your FIFO for TLAST
3. After you export HDF to SDK, generate a BSP for your R5_0 (New BSP, Name R5_0_BSP, CPU psu_cortexr5_0, OS standalone)--Finish--No additional libraries.
4. Use the axi_dma_? example code in the corresponding system.mss. Import example, select xaxidma_example_sg_intr.c.
5. Study the code. Pay attention to MEM_BASE_ADDR defined. (This is just an example, you'll probably want to use malloc and cache align your buffers on a real project).
6. Download and have fun.
Note: I have not done SG on the R5 before, but I suspect you'll get it working with this recipe.
You could delete your block diagram from your project, and run the attached tcl script instead. It is using S_AXI_LPD. It is for 2018.3 (same as your tcl script), but I'd also upgrade to 2019.1 if you can. The attached script will allow you to use VLA as well, to see what is going on in hardware.
01-27-2020 03:21 AM
Thanks for guiding me howeever I have two problems right now.
1) I am not observing output in serial terminal. (Not even hello world output on the serial terminal). I have checked the your .tcl script and UART is already configured.
2) The ILA is not detected and it is showing the warnings as free running clock is required.
Regarding the SDK file I have the following configurations.
#define DDR_BASE_ADDR XPAR_PSU_DDR_0_S_AXI_BASEADDR
#define MEM_BASE_ADDR (DDR_BASE_ADDR + 0x1000000)
In my case DDR_BASE_ADDR is 0x00000000,
Please suggest me on this.
What about s2mm and mm2s interrupts? When these two will be generated?
01-27-2020 02:20 PM
Study the code previously specified, and test. Also it sounds like your build might not be right if you're not seeing an ILA. Did you delete your block diagram, and use the script I posted instead? After deleteing it from the project and the diskdrive, go to your tcl console assuming you're in project mode gui, and type source c:/mydownloadpath/forPavan_bd.tcl.
Also, did you use the axi_dma_? example code in the R5_0 bsp' system.mss. Import example, select xaxidma_example_sg_intr.c. That will tell you when the interrupts are used. You shouldn't have a problem with any messages about a free running clock missing so I think you must have changed something, although I do not have a ZCU102 to test it on. Download FPGA from SDK, debug application in SDK, then go back to Vivado and launch the hardware manager.
01-30-2020 02:32 AM
Sorry for the delay.
I have used your method for ILA. It works. Thanks for that but my concern is all the signals are inactive in ILA capture.
What could be the possible reasons? Any input is highly valuable
Please find attached with the screenshots of ILA capture in Vivado
01-30-2020 05:39 PM
What was your trigger condition? Trigger on TVALID on your MM2AXI stream.