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Visitor darren
Visitor
1,079 Views
Registered: ‎12-03-2018

How to configure PS-PL master interface(AXI HPM FPD)?

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Hi, I am using zynq ultrascale+ mpsoc and vivado 2018.2.

I trying to connect my custom AXI bus to PS.

so I want to config AXI HPM FPD parameter. but I can find only data width select in Re-customize IP window.

how to configure IP width, address width, length width etc. ??

I can't use AXI Interconnect IP or AXI smartconnect IP.

can I modify config_mpsoc_zynq_ultra_ps_e_0_9.xci??(for example: change ID_WIDTH 16 to 4) 

<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_HPM1_FPD.ID_WIDTH">16</spirit:configurableElementValue>

 

where is maxigp0_wid?? I can't find write ID tag, PG201 and MPSoC IP.

there are only awid, bid, arid, rid.

thank you.

 

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Scholar jg_bds
Scholar
1,025 Views
Registered: ‎02-01-2013

Re: How to configure PS-PL master interface(AXI HPM FPD)?

Jump to solution

@darren wrote:

Hi, I am using zynq ultrascale+ mpsoc and vivado 2018.2.

     Been there; done that.

I trying to connect my custom AXI bus to PS.

so I want to config AXI HPM FPD parameter. but I can find only data width select in Re-customize IP window.

     That AXI interface is rather fixed, apart from data-width variation that you've already found you can change. You just need to enable the interface on the Zynq block in your IPI block diagram, and then hook-up to the new pin.

how to configure IP width, address width, length width etc. ??

     I'm not sure what "IP width" means. The address width is fixed at 40 bits, which is sufficient to address just about everything in the PSU. Length width (ARLEN & AWLEN?) is fixed at 8 bits--which supports the longest burst specified in AXI 4 (256 beats). "etc."? Umm... You'll have to get by with 16 USER and 16 ID bits...? 

I can't use AXI Interconnect IP or AXI smartconnect IP.

     Ohhh, yes you can. The AXI Interconnect will automatically map all of the signals your IP needs at the AXI port of the PSU, truncating what needs to be truncated, and tying-off any unused signals. Otherwise, you'll have to do that all yourself. (To be honest, I'm not sure if direct connection is even allowed.)

can I modify config_mpsoc_zynq_ultra_ps_e_0_9.xci??(for example: change ID_WIDTH 16 to 4) 

     That's NOT recommended.

<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_HPM1_FPD.ID_WIDTH">16</spirit:configurableElementValue>

 where is maxigp0_wid?? I can't find write ID tag, PG201 and MPSoC IP.

there are only awid, bid, arid, rid.

     WID was banished from the AXI world between AXI3 and AXI4.  (Turns out, WID usually was unnecessarily redundant.) That's another good thing AXI Interconnects do: they automatically map AXI3 and AXI4.

thank you.

     You're welcome. 


-Joe G.

 

1 Reply
Scholar jg_bds
Scholar
1,026 Views
Registered: ‎02-01-2013

Re: How to configure PS-PL master interface(AXI HPM FPD)?

Jump to solution

@darren wrote:

Hi, I am using zynq ultrascale+ mpsoc and vivado 2018.2.

     Been there; done that.

I trying to connect my custom AXI bus to PS.

so I want to config AXI HPM FPD parameter. but I can find only data width select in Re-customize IP window.

     That AXI interface is rather fixed, apart from data-width variation that you've already found you can change. You just need to enable the interface on the Zynq block in your IPI block diagram, and then hook-up to the new pin.

how to configure IP width, address width, length width etc. ??

     I'm not sure what "IP width" means. The address width is fixed at 40 bits, which is sufficient to address just about everything in the PSU. Length width (ARLEN & AWLEN?) is fixed at 8 bits--which supports the longest burst specified in AXI 4 (256 beats). "etc."? Umm... You'll have to get by with 16 USER and 16 ID bits...? 

I can't use AXI Interconnect IP or AXI smartconnect IP.

     Ohhh, yes you can. The AXI Interconnect will automatically map all of the signals your IP needs at the AXI port of the PSU, truncating what needs to be truncated, and tying-off any unused signals. Otherwise, you'll have to do that all yourself. (To be honest, I'm not sure if direct connection is even allowed.)

can I modify config_mpsoc_zynq_ultra_ps_e_0_9.xci??(for example: change ID_WIDTH 16 to 4) 

     That's NOT recommended.

<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_HPM1_FPD.ID_WIDTH">16</spirit:configurableElementValue>

 where is maxigp0_wid?? I can't find write ID tag, PG201 and MPSoC IP.

there are only awid, bid, arid, rid.

     WID was banished from the AXI world between AXI3 and AXI4.  (Turns out, WID usually was unnecessarily redundant.) That's another good thing AXI Interconnects do: they automatically map AXI3 and AXI4.

thank you.

     You're welcome. 


-Joe G.