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338 Views
Registered: ‎06-27-2018

How to guarantee PS DDR bandwith from a custom AXI master IP in the PL on a Zynq UltraScale+ device

Hello

a customer needs to have 8Gbps write speed from his custom AXI master IP in the PL.

He is targeting a LPDDR4 on the PS (similar hardware as on the Ultra96)

When a software task in the PS is running a memory intensiv application the write speed of the IP in the PL is affected.

There was a thread asking for the documentation of the PS DDR service registers which might be a solution:

https://forums.xilinx.com/t5/Embedded-Processor-System-Design/Zynq-UltraScale-PS-DDR-quantity-of-service-registers-for-AXI/td-p/886298

Can someone please give an update on this?

Thanks

Marco

 

 

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3 Replies
Moderator
Moderator
292 Views
Registered: ‎07-31-2012

Re: How to guarantee PS DDR bandwith from a custom AXI master IP in the PL on a Zynq UltraScale+ device

Hi marco.hoefle@avnet.eu ,

Please verify PS DDR (DDRC) register details in UG1087.

Regards

Praveen

 


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263 Views
Registered: ‎06-27-2018

Re: How to guarantee PS DDR bandwith from a custom AXI master IP in the PL on a Zynq UltraScale+ device

Hello Praveen,

thank you for your hint.

It is not clear to me how to use the DDRC registers for controlling the priority.

I looked at 

PCTRL_0 

PCFGW_0, is the wr_port_urgent_en what you mean?

PCFGQOS0_0 

PCFGQOS1_0 

PCFGWQOS0_0 

PCFGWQOS1_0 

 

Can you explain in more detail -  based on the memory overview below - how to ensure that for example S_AXI_HP0_FPD has priority?

Capture.PNG

 

Thank you

Marco

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Xilinx Employee
Xilinx Employee
236 Views
Registered: ‎09-01-2014

Re: How to guarantee PS DDR bandwith from a custom AXI master IP in the PL on a Zynq UltraScale+ device

DDR QoS settings in GUI will be presented in Advance Configuration page with new
node "DDR QoS Configuration" under advance configuration mode.
DDR QoS feature has already been supported starting from 2017.3 with using
"set_param pcw.enableddrqos {1}" TCL parameter.
The page will be mainly classified into two categories
1. AXI Port classification :
2. CAM Threshold level :

QoS programming will be written in separate proc in psu_init.c/tcl. The new proc name will be "psu_ddr_qos_init_data()".
Then you can find how these Qos registers are set.

Also you can change the QoS setting and use the system performance monitor to measure the performance.
https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842421/Zynq+UltraScale+MPSoC+-+System+Performance+Modelling



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