04-23-2019 11:26 PM
a customer needs to have 8Gbps write speed from his custom AXI master IP in the PL.
He is targeting a LPDDR4 on the PS (similar hardware as on the Ultra96)
When a software task in the PS is running a memory intensiv application the write speed of the IP in the PL is affected.
There was a thread asking for the documentation of the PS DDR service registers which might be a solution:
Can someone please give an update on this?
04-29-2019 03:18 AM
Please verify PS DDR (DDRC) register details in UG1087.
05-06-2019 12:09 AM
thank you for your hint.
It is not clear to me how to use the DDRC registers for controlling the priority.
I looked at
PCFGW_0, is the wr_port_urgent_en what you mean?
Can you explain in more detail - based on the memory overview below - how to ensure that for example S_AXI_HP0_FPD has priority?
05-07-2019 06:42 PM