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Contributor
Contributor
562 Views
Registered: ‎08-28-2017

How to handle the 2 clocks in PL (zynq 7020)

Hi Folks,

 

We are designing video pipeline for 27MHz write path into DDR through VDMA is 8 bit data width. reading the 16 bit data from DDR through VDMA with a 100MHz. Here we need know how to handle two clock domain ?

 

Please suggest me.

 

Thanks and Best Regards

Vinod Sajjan

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2 Replies
Mentor hgleamon1
Mentor
525 Views
Registered: ‎11-14-2011

Re: How to handle the 2 clocks in PL (zynq 7020)

A FIFO perhaps?

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"That which we must learn to do, we learn by doing." - Aristotle
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Moderator
Moderator
487 Views
Registered: ‎11-09-2015

Re: How to handle the 2 clocks in PL (zynq 7020)

Hi @vinod.sajjan,

 

The VMDA will handle the 2 clock domains.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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