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Adventurer
Adventurer
6,957 Views
Registered: ‎05-01-2012

How to have a version number for the FPGA project?

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I'm a little new to FPGA design, I'm normally a software engineer.  With software, this topic is solved, there's lots of ways to put a version number in software.  My company puts version numbers in each individual HDL module, but since I need to know what HDL modules are even in the FPGA before I can try and check their version, is there some way to have a version number attached to the FPGA project as a whole, that can be readable from software?  Maybe some register in the Zynq that's always there and the Vivado project can be configured to set to a particular value?  It's fine if I have to manually set the version.  Or do we have to make a special "version" HDL module that will always be at a particular address with the project version?  Has anyone solved this problem in an elegant way?

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Xilinx Employee
Xilinx Employee
10,498 Views
Registered: ‎07-31-2012

Re: How to have a version number for the FPGA project?

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You can give a register in the hardware and write/read it from teh SW using the processor. As such there is no other way to assign a version number to a design which can be readable from the processor as i know.
Thanks,
Anirudh

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Xilinx Employee
Xilinx Employee
6,933 Views
Registered: ‎10-24-2013

Re: How to have a version number for the FPGA project?

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HI @jschell

https://www.xilinx.com/support/documentation/application_notes/xapp1165.pdf

The above documents has information related to Vivado based version control mechanism. Hope this helps.

Thanks,Vijay
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Adventurer
Adventurer
6,926 Views
Registered: ‎05-01-2012

Re: How to have a version number for the FPGA project?

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I wasn't asking about version control of the source code. I'm asking about getting a version number on the target while it's running. I can compile a version number into my application, can I do something similar with an FPGA project?

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Xilinx Employee
Xilinx Employee
6,919 Views
Registered: ‎08-01-2008

Re: How to have a version number for the FPGA project?

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It seems you are asking about design runs

check the *.runs file in your proejct.

You can also use commends


current_run [get_runs synth_1]

check this post as well
https://forums.xilinx.com/t5/Design-Entry/Vivado-and-version-control/td-p/347941/page/6
Thanks and Regards
Balkrishan
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Xilinx Employee
Xilinx Employee
10,499 Views
Registered: ‎07-31-2012

Re: How to have a version number for the FPGA project?

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You can give a register in the hardware and write/read it from teh SW using the processor. As such there is no other way to assign a version number to a design which can be readable from the processor as i know.
Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
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Scholar austin
Scholar
6,882 Views
Registered: ‎02-27-2008

Re: How to have a version number for the FPGA project?

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js,

 

There are dedicated user bytes available in the configuration engine you may assign a value to.  Or you can create a register and assign an INIT value.  These solutions both put that unique number in the bitstream file.  You could then do a secure hash on the bitstream, and keep that value in your records to positively identify it.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Xilinx Employee
Xilinx Employee
6,872 Views
Registered: ‎08-02-2011

Re: How to have a version number for the FPGA project?

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It's pretty common to just put a memory-mapped register in in the PL that holds a version number for a module (or entire design if you wish). If you look at some of Xilinx video IP, for example, you'll find a version register in the memory map. I've seen many customers do similar things.

www.xilinx.com
Teacher muzaffer
Teacher
6,845 Views
Registered: ‎03-31-2012

Re: How to have a version number for the FPGA project?

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@jschell it's certainly possible to add version to fpga. Assuming you have any axi slaves, you can just add a register to one of them which carries the git commit id (or any other similar tag) and any other information you want about the build. In my case, I have a master controller slave which has a 32 bit commit id (ie 8 hex digits of the last commit) and the UTC time the image is built which can be queried at run-time.

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Explorer
Explorer
2,871 Views
Registered: ‎09-13-2011

Re: How to have a version number for the FPGA project?

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What we need is an auto-updated version number that can be used in VHDL/Verilog.

Since there's no support for this in the LRMs as far as I know, I would suggest Xilinx to implement support for something like this (VHDL):

constant c_build_no   : natural;

-- synthesis translate c_build_no to BUILD_NO

It's ok that the number is incremented on each synthesis and not only for implementations. It probably wont work for non-project mode but that's not so important as build systems easily can include means to auto-update a package/.h file.

Another way that could work in non-project mode would be to add a command in the constraints file but I'm not too keen on having the tool to auto-update my constraints file.

set_property BUILD_NO 0x00000101

 

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2,839 Views
Registered: ‎01-08-2012

Re: How to have a version number for the FPGA project?

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I would prefer that Xilinx NOT add yet another non-portable, non-standard VHDL "enhancement", particularly as everything you wish to do can be done with the existing tools.

For example, (most of) my larger FPGA designs contain registers so that software can read:

  • Manually updated version numbers
  • Automatically updated version numbers (increment every build)
  • Automatically updated version numbers (increment every build, guaranteed to be unique across all projects at that company)
  • Timestamp (in UNIX 32 bit format)
  • Source code management revision number

This works in VHDL, Verilog, Xilinx, Altera.

BTW, I only use a non-project scripted flow, which gives my scripts the ability to interact with just about anything on my local network.

2,834 Views
Registered: ‎06-29-2015

Re: How to have a version number for the FPGA project?

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I agree. The original question was asked because we thought there may already be a dedicated register that could be used to read version information.

If you use a scripted build then you are free to "compile" in a build version in to a custom memory mapped register that gives you all the freedom and flexibility that you may require.

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Xilinx Employee
Xilinx Employee
2,818 Views
Registered: ‎02-01-2008

Re: How to have a version number for the FPGA project?

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There is a register I've used in the past for revision. In the configuration logic, there is a USR_ACCESS register that can be instantiated in your design. Logic can read the 32bit value of this register, and the contents of the register is either automatically populated with a timestamp, or can be populated with a user value during bitstream creation.

Nice thing with this reg is that any updates to bram via merging with the bitstream can be tracked by a version.

Check the configuration user guide for the device you are targeting.

I do agree that this is not a catch all and there is still a place for a revision register that is updated during TOP synth. Or, carefully crafted hdl could create a design where tcl could be used to modify a revision register via the tcl hooks post implementation.

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Explorer
Explorer
2,801 Views
Registered: ‎09-13-2011

Re: How to have a version number for the FPGA project?

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Allan I'm not forcing you to use it. It would be a feature that would be useful when doing small project mode flows not interfering with non-project scripted flows for larger projects. Just another item on your list.
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Scholar drjohnsmith
Scholar
2,792 Views
Registered: ‎07-09-2009

Re: How to have a version number for the FPGA project?

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An old old problem,

 

Other tools, can have a 'variable' auto incremented on each run,  put in a time date stamp etc.

 

Unfortunately , 

   xilinx have not implemented this 'yet'

There are various 'answers' on the forum and web, 

    bottom line for Xilinx is that unless you are script based, its not possible,

 

 

 

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2,721 Views
Registered: ‎01-08-2012

Re: How to have a version number for the FPGA project?

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    Allan I'm not forcing you to use it.

@tsjorgensen Sure, it would be a nice-to-have feature.  But I'm actually more concerned about Xilinx spending their limited development resources on things such as bugs or VHDL-2008 coverage or high level synthesis of VHDL (not C).

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Xilinx Employee
Xilinx Employee
2,593 Views
Registered: ‎02-01-2008

Re: How to have a version number for the FPGA project?

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It is possible when using the gui if you use the tcl.pre and/or tcl.post options for implementation or bitstream to change a register value post implementation.

Or, you can set BITSTREAM.Config.USR_ACCESS to TIMESTAMP during bitstream creation and add an axi wrapper around the jtag USR_ACCESS register.

For post implementation modifications, You would create your version register by instantiating LUT1s, and then use tcl.post script to modify the LUT INIT value to match your required version.

I tried using tcl.pre on synth to update a verilog .h file with a version value but tcl.pre appears to be ran after synthesis has started, so after synthesis, Vivado gui still thinks synth is out of date. You could possibly force an update call via tcl.pre for implementation but I didn't try that. Or, use a user definable function in the gui to call a script that updates the verilog .h but that would be prone to error if you forgot to run it before synth.

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Scholar drjohnsmith
Scholar
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Registered: ‎07-09-2009

Re: How to have a version number for the FPGA project?

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You can't use tcl.pre if the serial number is in a file . Assuming the serial number is in the project, then tcl.pre is run after the project has been checked for file changes. SO after the project has been run, the file with the serial numbe rin is now marked as out of date, as its changed, so the project is out of date.

This is the BIG problem with the xilinx tcl.pre, un like other tools , which run a tcl.pre equivalent before the files are checked .

Its a LONG running bug, which Xilinxs answer is to run totally from a TCL script, not the GUI.....

One day Xilinx will listen and add a tcl_pre.pre or something that the gui runs before the files are elaborated...

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Xilinx Employee
Xilinx Employee
2,218 Views
Registered: ‎02-01-2008

Re: How to have a version number for the FPGA project?

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Correct, you cant use pre.synth tcl to change a header file, but you can use pre.synth to assign a generic/parameter that then sets the value in hdl.

Synth tcl.pre would contain something like:

set_property generic {DEFINE_MY_VAL=32'h0000AAAA} [current_fileset]

And Verilog would be:

 

module top #(
        parameter DEFINE_MY_VAL = 0
) (
  input wire reset,
  input wire user_si570_sysclk_clk_n,
  input wire user_si570_sysclk_clk_p,
  output wire [31:0] version_syn
);

    assign version_syn = DEFINE_MY_VAL ;

In Synth tcl.pre, you can also do things like:

  set version [clock format [clock seconds] -format "32'h%d%H%M%S"]

 

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Voyager
Voyager
2,191 Views
Registered: ‎02-01-2013

Re: How to have a version number for the FPGA project?

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Why not pile on...?

---------------------------------------------------------------

Me? I prefer manual version/revision control in my designs. Every embedded design I do gets an IP called "Core Regs". My original Core Regs IP was generated long ago using "Create and Package New IP" wizard.

The IP contains 8 registers: a read-only ID register, 3 general-purpose write/read Control registers, 3 read-only Status registers, and a read-only Version/Revision Register. The Verilog parameters that connect to the ID and Ver/Rev registers are exported to the top-level as customization properties, so those can be changed without re-building the IP.

2019-01-08_18-43-34.jpg

The ID register gets a code that identifies the project and the particular FPGA, so the design can be confirmed as appropriate at a glance. It's a good way, for instance, to distinguish an original design that was targeted for a reference design, like a ZC706, versus the migrated one that was targeted for the actual prototype.

The Version/Revision register is the 'tracking' register. The 4 bytes of that register are treated as such: 1) official release number, 2) FPGA type, 3) FPGA version, and 4) Revision.

"FPGA type" refers to the purpose of the particular design. My Core Reg 'spec' currently accounts for 7 different FPGA 'types': Pinout, Interface, Functionality, Test, Operational, Diagnostic, and Dummy. 

"FPGA version" changes based on the breath of a particular type of design.  e.g., an Interface design that's meant to test 1 Ethernet port might be V0, and another design that tests all Ethernet ports might be V1.

Revision is the second hand of the register. :-) It gets bumped every time someone other than me gets a copy of a design. So even though it could have take me 13 iterations to get that &@%$# IP working, this byte might only get upped at the end, prior to dissemination.

-Joe G.

 

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Scholar drjohnsmith
Scholar
2,161 Views
Registered: ‎07-09-2009

Re: How to have a version number for the FPGA project?

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Whilst were talking about verision numbers in general.

 

I like to have something automatic in there,

a time / date stamp is very useful,

Being a consultant, I'm giving the game away here, but ,

   the number of times I see companies that have something that has worked for years and now doesn't, and they get me in,

      and it turns out some one has done a re compile on a new machine / new version of the tools , etc etc...  

I feel a little guilty charging , but only a little........

 

 

 

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