UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer mohdamir
Observer
4,179 Views
Registered: ‎07-15-2010

How to initiate write operation in Master PLB?

Jump to solution

Hello everyone.

 

I want to create an IP core which use Master PLB (MPLB) as bus interface. So I created IP core from "Create or Import Peripheral...". Then I used "User logic master" by put tick in IPIF Services. After it finish, a user_logic.vhd was created. In order to initiate write operation, I tried to use the step given as shown below:

 

-- 1. write 0x40 to the control register

-- 2. write the target address to the address register

-- 3. write valid byte lane value to the be register

-- - note: this value must be aligned with ip2bus address

-- 4. write 0x0004 to the length register

-- 5. write 0x0a to the go register, this will start the master write operation

 

I would like to know, what is the "valid byte lane value" that should be put in step #3. And second thing is, how can I send the data from Master PLB to other IP core.

 

Thank you.

0 Kudos
1 Solution

Accepted Solutions
Observer mohdamir
Observer
5,102 Views
Registered: ‎07-15-2010

Re: How to initiate write operation in Master PLB?

Jump to solution

Thank you for your help.

 

Now I know how to do it, basically there is a folder called "driver" once we created our new IP. The folder has a sample code on how to use PLB master/slave.

 

Cheers

0 Kudos
3 Replies
Observer thobmei
Observer
4,147 Views
Registered: ‎05-28-2010

Re: How to initiate write operation in Master PLB?

Jump to solution

"valid byte lane value" sounds like the the length of the Data Package.

 

Its might an good idea to use an FSM to Write to another core that performs the steps.

2. write the target address to the address register << that sounds like BASE_ADRESS

 

Take a closer Look in the Ipif default Template to understand how the writing works ...

 

Best

tobias

 

 

taken form the Default template:

 

  --USER logic implementation added here

  ------------------------------------------
  -- Example code to demonstrate user logic master model functionality
  --
  -- Note:
  -- The example code presented here is to show you one way of stimulating
  -- the PLBv46 master interface under user control. It is provided for
  -- demonstration purposes only and allows the user to exercise the PLBv46
  -- master interface during test and evaluation of the template.
  -- This user logic master model contains a 16-byte flattened register and
  -- the user is required to initialize the value to desire and then write to
  -- the model's 'Go' port to initiate the user logic master operation.
  --
  --    Control Register     (C_BASEADDR + OFFSET + 0x0):
  --       bit 0    - Rd     (Read Request Control)
  --       bit 1    - Wr     (Write Request Control)
  --       bit 2    - BL     (Bus Lock Control)
  --       bit 3    - Brst   (Burst Assertion Control)
  --       bit 4-7  - Spare  (Spare Control Bits)
  --    Status Register      (C_BASEADDR + OFFSET + 0x1):
  --       bit 0    - Done   (Transfer Done Status)
  --       bit 1    - Busy   (User Logic Master is Busy)
  --       bit 2    - Error  (User Logic Master request got error response)
  --       bit 3    - Tmout  (User Logic Master request is timeout)
  --       bit 2-7  - Spare  (Spare Status Bits)
  --    Addrress Register    (C_BASEADDR + OFFSET + 0x4):
  --       bit 0-31 - Target Address (This 32-bit value is used to populate the
  --                  IP2Bus_Mst_Addr(0:31) address bus during a Read or Write
  --                  user logic master operation)
  --    Byte Enable Register (C_BASEADDR + OFFSET + 0x8):
  --       bit 0-15 - Master BE (This 16-bit value is used to populate the
  --                  IP2Bus_Mst_BE byte enable bus during a Read or Write user
  --                  logic master operation for single data beat transfer)
  --    Length Register      (C_BASEADDR + OFFSET + 0xC):
  --       bit 0-3  - Reserved
  --       bit 4-15 - Transfer Length (This 12-bit value is used to populate the
  --                  IP2Bus_Mst_Length(0:11) transfer length bus which specifies
  --                  the number of bytes (1 to 4096) to transfer during user logic
  --                  master Read or Write fixed length burst operations)
  --    Go Register          (C_BASEADDR + OFFSET + 0xF):
  --       bit 0-7  - Go Port (Write to this byte address initiates the user
  --                  logic master transfer, data key value of 0x0A must be used)
  --
  --    Note: OFFSET may be different depending on your address space configuration,
  --          by default it's either 0x0 or 0x100. Refer to IPIF address range array
  --          for actual value.
  --
  -- Here's an example procedure in your software application to initiate a 4-byte
  -- write operation (single data beat) of this master model:
  --   1. write 0x40 to the control register
  --   2. write the target address to the address register
  --   3. write valid byte lane value to the be register
  --      - note: this value must be aligned with ip2bus address
  --   4. write 0x0004 to the length register
  --   5. write 0x0a to the go register, this will start the master write operation
  --
  ------------------------------------------

0 Kudos
Observer thobmei
Observer
4,139 Views
Registered: ‎05-28-2010

Re: How to initiate write operation in Master PLB?

Jump to solution
0 Kudos
Observer mohdamir
Observer
5,103 Views
Registered: ‎07-15-2010

Re: How to initiate write operation in Master PLB?

Jump to solution

Thank you for your help.

 

Now I know how to do it, basically there is a folder called "driver" once we created our new IP. The folder has a sample code on how to use PLB master/slave.

 

Cheers

0 Kudos