How to program in the correct memory when using Microblaze?

[kasturis]

I am using a KC705 evaluation board with Kintex-7. I am trying to interface an external DAQ board via the FMC connector. The DAQ manufacturer provided the HDL required for interfacing and also the software project to be implemented in SDK (since the design implements Microblaze microprocessor).

We first followed the procedure below to program the FPGA for this:

1. Synthesize, Implement and Generate bitstream for the HDL project in Vivado.
2. Import the .hdf file into SDK, open the SDK project given by the manufacturer, build it and generate linker script with code, data and heap+stack memory set to sys_ilmb_cntrl_Mem_sys_dlmb_cntrl_Mem (refer figure 1) which has total size 128KB. Heap and stack size are by-default 1KB each, and we let them be.
3. We program the FPGA by Xilinx -> Program FPGA -> Select the .bit file from Vivado's HDL project and .elf file from the current SDK project.
4. However, we encounter a lot of run-time errors and behaviour is erratic.

However this page states that the heap size should be at least 1MB when microblaze is used (figure 2), else it would result in erratic behaviour. But we cannot achieve this unless we choose a different memory from the list (larger than 128KB). I am not aware of the correct flow/steps to do that. Can someone please guide me on how to do this? Thank you.

Figure 1. Generate linker script window.

Figure 2. We are instructed to use at least 1MB heap size

[stephenm]

Can you explain what your erratic behaviour is? 

Does your application require a lot of heap and stack.

[kasturis]

The erratic behaviour is seen in the external board we are trying to interface (FMCDAQ2 by Analog Devices), and not in the FPGA itself.

The manufacturer (Analog Devices), who developed the embedded software for microblaze says that we require 1MB heap size (fig. 2 in my original post).

[stephenm]

Have you tried place all sections into your DDR, and increase the heap and stack.

[kasturis]

Hi, thanks for the response.

We have tried burning all the sections into DDR memory (fig. 1), but it did not work. We followed these steps:

1. Generate linker script (fig. 1)

2. In SDK: Xilinx > Program FPGA > Select .bit, .bmm and .elf files.

But I am not sure whether it has been done correctly. In particular I am not sure:

1. Which .bit file to select? There is a .bit file in /<hdl_proj>.sdk/, in /<hdl_proj>.runs/impl_1/ and possibly other subfolders of the project provided by the manufacturer. Which of these .bit files is to be selected?

2. Which .bmm/mmi file to select. Similar to the above point, there are multiple .bmm and .mmi files in several subfolders of the project. Which of these is to be selected?