03-26-2018 02:35 AM
I am trying to use AXI Uartlite IP to send some data to COM port of Nexys video board. I went through PG142 and PG155 product guides and figured out the way to initialize different ports of the IP.
The AXI Uartlite is configured as follows.
CLK 1MHz, baud rate 9600, data bits 8
S_AXI_wvalid <= '1';
S_AXI_wstrb <= '1';
S_AXI_awvalid <= '1';
S_AXI_aresetn <= '1';
S_AXI_awaddr <= "0100";
S_AXI_wdata <= "00000000000000000000000001010011";
When I simulate, the TX port output of AXI Uartlite just remains ‘X’ state instead toggling as per S_AXI_wdata. I have simulated up to 4 seconds and ll the values are initialized from the beginning of simulation.
Am I missing any configuration setting? or anything needs to be carried out to get the data at TX port ?
Help is much appreciated.
03-26-2018 02:58 AM - edited 03-26-2018 03:40 AM
In my opinion you are not driving the axi4lite signals properly.
The UARTLite comes with an example_design. Study that and make sure you understand how the test-bench in this eg_design is driving data into this core. Later apply this concept to drive your own data into the core.
Read Chapter 5 of the UARTLite spec.
Read the AXI4Lite spec.
03-26-2018 03:29 AM
Please try using AXI UART lite IP example design and simulate it to understand the AXI signals behaviors.
04-02-2018 11:18 PM
04-03-2018 01:13 AM
i kept it high from the starting which resulted in output high impedance state.
Glad that you found the error.
yes, one must always respect *reset_n, which must be low for a few clk cycles before it can be de-asserted.
04-03-2018 03:15 AM
Please close the thread if you resolved the issue by marking the solution.