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Observer fpgause
Observer
10,339 Views
Registered: ‎11-13-2010

Re: How to use larger BRAM in a MicroBlaze project?

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Thanks it was helpful i tried to use multiple brams but the resources issues came so this technique i cannot use further ......About offset initially i had given a less offset between firmware and video and Ethernet was showing errors but when i increase that offset the error was removed ........In my model to be sure the data is there in DDR memory i display it on projector along with send on Ethernet .It displays on projector but Ethernet doesn't work ........So iam curious whether it possible too keep both firmware and also use for video ? also can u suggest something from ur experience 

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Explorer
Explorer
10,324 Views
Registered: ‎05-30-2008

Re: How to use larger BRAM in a MicroBlaze project?

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@fpgause wrote:

Thanks it was helpful i tried to use multiple brams but the resources issues came so this technique i cannot use further ......About offset initially i had given a less offset between firmware and video and Ethernet was showing errors but when i increase that offset the error was removed ........In my model to be sure the data is there in DDR memory i display it on projector along with send on Ethernet .It displays on projector but Ethernet doesn't work ........So iam curious whether it possible too keep both firmware and also use for video ? also can u suggest something from ur experience 


 

I am unsure exactly what this means:

 

"So iam curious whether it possible too keep both firmware and also use for video ? also can u suggest something from ur experience"

 

I think I understand you want to output video on both the DVI port or something and also send the video data over ethernet. I have done similar things. Once you have the video data in memory - it is there so you can read it out multiple times and send it multiple places.

 

For a current design I am working on, we have two frame buffers due to timing issues. I get input video and buffer frames in one memory location. I then read this out and send out to a custom video interface while simultaneously writing it into a new frame buffer. This allows the frames I just read to be replaced with incomming data while still having those frames available to output on another interface - in this case a custom HDMI module. HDMI requires 60 Hz and i only have 30 coming in so I duplicate the frames in the second frame buffer.

 

At some point you can run into memory bandwidth limitations, but it takes a lot to do this. If you read all memory with the processor and not just with a firmware memory controller - access will likely be slower. I adapted one of the DVI reference designs and wrote every pixel with the processor and it was really slow.

 

I have had some issues with getting ethernet to work also. You'll figure it out - it just takes some time.

 

I hope this helps. Please clarify what your problem is and what you are trying to accomplish if this does not help.

 

Also you may want to post this in a new and more appropriate thread if I cannot help you

 

Josh

 

 

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Observer fpgause
Observer
10,314 Views
Registered: ‎11-13-2010

Re: How to use larger BRAM in a MicroBlaze project?

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The task is to send streaming data from camera to PC through  Ethernet ....i was asking if i kept the firmware in external memory and also use it for video buffering and iam sure no memory overlaps occur, so am i going correct ?............

 

About dvi out i used it  because just to check whether  video  data is coming and to be convinced that it is not being blocked on the way and yes it was displaying on projector but the same data was not being transferred on Ethernet (dvi out is not required in final model ) ......

 

actually iam left with very less time if u can give me some guidance it would be helpful so without wasting my time i can work in right areas ....

thanks

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Explorer
Explorer
10,293 Views
Registered: ‎05-30-2008

Re: How to use larger BRAM in a MicroBlaze project?

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@fpgause wrote:

The task is to send streaming data from camera to PC through  Ethernet ....i was asking if i kept the firmware in external memory and also use it for video buffering and iam sure no memory overlaps occur, so am i going correct ?............

 

About dvi out i used it  because just to check whether  video  data is coming and to be convinced that it is not being blocked on the way and yes it was displaying on projector but the same data was not being transferred on Ethernet (dvi out is not required in final model ) ......

 

actually iam left with very less time if u can give me some guidance it would be helpful so without wasting my time i can work in right areas ....

thanks


 

I have done a similar design and actually hired a Xilinx person to help us with the design at one point because of issues with the lwip stack. We considered using something like the TREK (?) stack but realized it was not necessary if lwip was used in raw mode instead of sockets mode. I also ended up using UDP instead of TCP.

 

Are you using compressed video or raw video? In other words: what throughput do you need on the ethernet port?

ie: 640x480 x 3 bytes/pixel or something like that - whatever your dimensions and pixel 'size' are. You also have to take into account how your packets are packaged up. A 24 bit pixel might be represented as an integer/u32 taking 32 bits / 4 bytes and then having a header around a packet with a handful of pixels in it. All of this will increase your need for throughput even more.

 

I was streaming a MPEG4 stream after the live video input was compressed using the Xilinx MPEG4 core (that was a nightmare getting the codec to work).

 

I decided to try to conform to some sort of normal video streaming by using a basic implementation of RTP and I used VLC (VideoLan Player) as my receiver. I was able to just send the MPEG4 stream and VLC could read it since it can read just about anything. This would not work for any other player probably. Your design will likely be different than this, but wanted to share what I did.

 

It was a lot of work to get the ethernet figured out. This was a few years ago and the ethernet core is hopefully better developed at this point.

 

I ended up using a firmware DMA engine to write packet data to a known DDR buffer location where the processor then wrote the packet header info and told the lwip/temac to send it. I forget exactly, but this avoided a lot of extra memory accesses. Without this, the MPEG4 encoder would have output the data and something would have to write it to memory. Then the processor would read it out of memory, packetize it and write it back into memory for the lwip/temac to then read out again and send over the wires. Something like that. Please remember it has been a few years since I worked on this project.

 

Side note:

I used an ML507 board and used sysAce to load my firmware. If you have a custom board you need a PROM or something to store the executable. The executable (C code into elf file) is separate from the firmware (vhdl/verilog into bit file) so since you are storing it in DDR you must first load the FPGA and then load the code into DDR - the FPGA loading process will not accomplish this. This is why I prefer the BRAMs if you can get the software design to fit because then (after "initialize bitstream with processor data") the elf file is loaded in the BRAMs and the FPGA load will include the executable. No need for a bootloader.

 

My main function in my processor code controlled the firmware and after initialization just ran in a while(1) loop. It would:

 

While(1){

Check if DMA done ("packet" memory populated with incoming data)

If done start another packet DMA into a second buffer and call send_packet() function

// alternate packet buffers

}

 

Here is where I would go from here:

 

1. Determine your necessary byte throughput and convert to Mbits/sec

- Can your Ethernet port handle this? 10/100/1000

 

2. Create a simple program to test maximum throughput in your configuration

// decide what packet size you want (try to match the fragment size of 1400 or whatever it is)

While(1){

send_udp/tcp_packet();

}

// Use some sort of receiver that will tell you how much data is being received on the other end

// I used VLC becasue it will tell you how much data is coming through even if it cannot decode it

// VLC may be able to decode your RAW video - unsure

 

3. If you cannot send/ receive ethernet traffic - debug this first and make sure you can send

 

4. Once you can send, it is likely your maximum throughput will be far below the throughput you need.

- Tweak settings until you can get it to go fast enough

- UDP vs TCP

- RAW vs Sockets mode

- Packet size (check to see if packets are fragmented - this will slow you down)

- (I think Ethernet will send fixed size packets regardless of what you throw at it - unsure)

- Think about what is the bottleneck (Are you reading from memory? Send a fixed value to avoid this)

 

5. Determine how you are packetizing your data

- I used basic RTP

- Create you own packet definition (packet number or something like that for receiver to know if out of order)

- Maybe just raw - no header info - depending on what your receiver needs or can handle

- I suggest at least packet number since UDP is likely necessary to get the throughput you need

- UDP may deliver out of order, packets may get lost, receiver must drop a frame

 

Please let me know if you need anymore clarification or suggestions.

 

Josh

 

 

 

 

 

 

 

 

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Observer fpgause
Observer
10,279 Views
Registered: ‎11-13-2010

Re: How to use larger BRAM in a MicroBlaze project?

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Thanks Josh it was helpful

Now what i have done is that i send a video of 160 x120 @25 fps from PC(MATLAB ) to FPGA ,save in external memory and receive it back it  on FPGA and it was working fine ........

 

About compression codecs i was unable to complete i did just intra frame compression and iam planning to develop a customized media player at PC to decompress that video .....

 

About through put u r right my data incoming is greater then output but to balance that iam decreasing the resolution and skipping some frames (camera resolution is 720 x 480 @ 50 fps and iam working on 25 fps to decrease data).....

 

The core iam using is Ethernet mac lite  and the board is video starter kit 3400 DSP  and protocols are tcp/ip protocols ...

.

so i have confirmed till know that my ethernet is working but when i send streaming video instead of offline it doesnot work what should be the next step ....

About DMA ,i have directly connected Ethernet to PLB and not used any DMA so is it  required to use and how ?

Thanks 

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Explorer
Explorer
10,260 Views
Registered: ‎05-30-2008

Re: How to use larger BRAM in a MicroBlaze project?

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"

so i have confirmed till know that my ethernet is working but when i send streaming video instead of offline it doesnot work what should be the next step ....

About DMA ,i have directly connected Ethernet to PLB and not used any DMA so is it  required to use and how ?

 

"

 

In your Matlab test, were you sending video data to the FPGA over the Ethernet?

 

How was this offline? Because you were never sending the video data out over Ethernet - just putting it in memory and reading it back?

 

Take this same test setup and then read it back from memory and send over Ethernet. Have you tested Ethernet sending or just receiving?

 

DMA is not necessary and complicated. My colleague created a custom memory controller that was a DMA engine. I would not want to go there unless you need to crank the bandwidth way up. Dma was not connected to the Ethernet mac but rather moved data around in memory without the use of the processor to make thing faster.

 

I don't understand what "it does not work" means. What are you doing and what doesn't work?

Are you putting video data in memroy and reading it back? And then trying to send over Ethernet?

Do you get data over Ethernet but it is not right? Do you not get any data? Are you not trying to send it?

How are you getting video in? Does your video out depend on getting video in or will it read out blank memory if nothing comes in? Could your frame dropping/resizing be the issue?

 

Do a test and send something over Ethernet. If this works, send your video data in the same way.

 

I can't help if I don't know what you are doing and what is not working. It is often tricky to figure out what is not working, but I can't figure that out for you. I might be able to make a suggestion if you can tell me exactly what is not working.

 

Trace the datapath to figure out exactly where the data is stopping.

 

Chipscope and the crappy software debugger that Xilinx provides have been very valuable to me in debugging tricky things like this. It can be much more revealing than the guess and check method.

 

Josh

 

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Observer fpgause
Observer
10,249 Views
Registered: ‎11-13-2010

Re: How to use larger BRAM in a MicroBlaze project?

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My project is to send the video capture from camera to PC through Ethernet ..........

To check the speed of connection i have echoed back a video (from PC to fpga and then fpga to PC) and verified my results but it is not required it is just for testing purpose .....

What i have to do now is to send the video data capture from camera through Ethernet to PC but the model which i made is not working means hyper terminal is showing "Network interface is established " but it is not telneting at PC site means it is not opening connection or sending any data  to PC......

so iam guessing what can be the problem ?........(it is verified that the video  data is coming and being stored in external memory of FPGA)

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Explorer
Explorer
10,214 Views
Registered: ‎05-30-2008

Re: How to use larger BRAM in a MicroBlaze project?

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@fpgause wrote:

My project is to send the video capture from camera to PC through Ethernet ..........

To check the speed of connection i have echoed back a video (from PC to fpga and then fpga to PC) and verified my results but it is not required it is just for testing purpose .....

What i have to do now is to send the video data capture from camera through Ethernet to PC but the model which i made is not working means hyper terminal is showing "Network interface is established " but it is not telneting at PC site means it is not opening connection or sending any data  to PC......

so iam guessing what can be the problem ?........(it is verified that the video  data is coming and being stored in external memory of FPGA)


 

I really can't know what is not working in the Ethernet design. Try to figure out what is different between what you have and your test system. I have frequently started a new project and merged in other working code to get things working. Sometimes it can be hard to find the issue.

 

This is what I would do if I got stuck on the ethernet not working:

 

1) Try to find anything different in the ethernet core or settings or code that is different from the test system.

2) If you find a difference - make them the saem and see if that fixes it

3) If you cannot find a single difference - copy the test system project and then insert the camera interface and then test

4) Surely it will take a little effort to merge these together so that both parts work, but I have gotten stuck many times and been unable to figure out why a seemingly identical project behaves differently than another that appears the same.\

5) Things to compare:

MHS file (temac instantiation and parameters, ensure clocks, resets are correct - I've had resets inverted before)

xparameters.h (temac addresses, possible settings, etc)

your c code (sending functions, addresses, test code)

 

Only you can debug your project - good luck.

 

Josh

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Adventurer
Adventurer
9,719 Views
Registered: ‎11-13-2008

Re: How to use larger BRAM in a MicroBlaze project?

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Hi Goran, Josh and others,

I've read this post and concluded that it possible to (1) connect multiple ILMB/DLMB controllers to the same microblaze LMB port, and further connecting these controllers to two separate bram_block (i.e. 64K and 32K each). The linker script trick should do the job as long as two controllers span a contiguous space. Is this the right understanding?

 

(2) Another option was to use one bram_block with LMB controller and another with PLB BRAM controller. What worked for Josh is having 2 PLB BRAMs contiguously addressed and LMB BRAM at a different address, so that he could place .text shared between two PLB BRAMs and something else like stack/heap in LMB.

I tried going with the first approach as it should free up PLB traffic, generated bitstream and testing rd/wr access to memory via XMD. What I observe is that writing to 0x1_0000 (64K) maps to 0x0, which means the MSB bits of the LMB bus from the microprocessor to both BRAM controllers is ignoring MSB bits.

Continuing further I set my linker to span all 96K memory, the app builds without issues and I can upload it via the debugger. I didn't try initializing the bitstream. The app does not work, of course, since the 2nd bram_block is not accessible even from debugger.
MEMORY
{
   ilmb_cntlr_1_dlmb_cntlr_1 : ORIGIN = 0x00000050, LENGTH = 0x00017FB0  // i.e. 96K
}

What am I missing?
EDK 9.2.02
Microblaze 7.10.a
dlmb_cntrl 2.10.a

 

See attached MHS. Note that both dlmb_cntlr_2 and dlmb_cntlr_1 attach to the same LMB interface dlmb_1 (same for ilmb controllers). Is this legal? Documentation says that LMB address on microblaze 7 is 32-bits, so it should be enought. It seems as though the tools are removing the address lines.

 

Thanks,

Victor

 

 

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Adventurer
Adventurer
9,715 Views
Registered: ‎11-13-2008

Re: How to use larger BRAM in a MicroBlaze project?

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Adding a screenshot of 2 bram_block's connected via the same LMB

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two_bram_connection.png
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Adventurer
Adventurer
9,200 Views
Registered: ‎11-13-2008

Re: How to use larger BRAM in a MicroBlaze project?

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I also tried the second approach with PLB BRAM controller:

- One LMB connected BRAM 64K    (0x00000000-0x0000FFFF)

- One PLB connected BRAM 32K     (0x00010000-0x00017FFF)

 

Again, writing to address 0x00010000 via XMD and reading back from 0 returns the same written result. So, the PLB BRAM is ignored. The values are always mapped to the first 64K.

 

XMD% mrd 0x0 3
   0:   88008800
   4:   00000000
   8:   B8080C40

XMD% mrd 0x10000 3
   10000:   88008800
   10004:   00000000
   10008:   B8080C40

 

XMD% mwr 0x00010000 0x12312312

XMD% mrd 0x0 3
   0:   0x12312312
   4:   00000000
   8:   B8080C40

XMD% mrd 0x10000 3
   10000:   0x12312312
   10004:   00000000
   10008:   B8080C40

 

MHS snippet:

----------

BEGIN microblaze
 PARAMETER INSTANCE = microblaze_1
 PARAMETER HW_VER = 7.00.a
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_FAMILY = virtex5
 PARAMETER C_INSTANCE = microblaze_1
 PARAMETER C_FSL_LINKS = 2
 BUS_INTERFACE IPLB = mb_plb_1
 BUS_INTERFACE DPLB = mb_plb_1
 BUS_INTERFACE SFSL0 = fsl_v20_2
 BUS_INTERFACE SFSL1 = fsl_v20_4
 BUS_INTERFACE DEBUG = debug_module_MBDEBUG_1
 BUS_INTERFACE DLMB = dlmb_1
 BUS_INTERFACE ILMB = ilmb_1
 BUS_INTERFACE MFSL0 = fsl_v20_1
 BUS_INTERFACE MFSL1 = fsl_v20_3
 PORT INTERRUPT = Interrupt_1
 PORT RESET = mb_reset
END

 

BEGIN bram_block
 PARAMETER INSTANCE = lmb_bram_1
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTB = dlmb_cntlr_1_BRAM_PORT
 BUS_INTERFACE PORTA = ilmb_cntlr_1_BRAM_PORT
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = ilmb_cntlr_1
 PARAMETER HW_VER = 2.10.a
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x0000FFFF
 BUS_INTERFACE SLMB = ilmb_1
 BUS_INTERFACE BRAM_PORT = ilmb_cntlr_1_BRAM_PORT
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = dlmb_cntlr_1
 PARAMETER HW_VER = 2.10.a
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x0000FFFF
 BUS_INTERFACE SLMB = dlmb_1
 BUS_INTERFACE BRAM_PORT = dlmb_cntlr_1_BRAM_PORT
END

BEGIN lmb_v10
 PARAMETER INSTANCE = ilmb_1
 PARAMETER HW_VER = 1.00.a
 PORT SYS_Rst = sys_bus_reset
 PORT LMB_Clk = sys_clk_s
END

BEGIN lmb_v10
 PARAMETER INSTANCE = dlmb_1
 PARAMETER HW_VER = 1.00.a
 PORT LMB_Clk = sys_clk_s
 PORT SYS_Rst = sys_bus_reset
END


BEGIN bram_block
 PARAMETER INSTANCE = bram_block_2
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = xps_bram_cntlr_2_PORTA
END

BEGIN xps_bram_if_cntlr
 PARAMETER INSTANCE = xps_bram_cntlr_2
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0x00010000
 PARAMETER C_HIGHADDR = 0x00017FFF
 PARAMETER C_SPLB_NATIVE_DWIDTH = 32
 BUS_INTERFACE SPLB = mb_plb_1
 BUS_INTERFACE PORTA = xps_bram_cntlr_2_PORTA
END

lmb_and_plb_bram_connections.png
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Xilinx Employee
Xilinx Employee
9,196 Views
Registered: ‎08-06-2007

Re: How to use larger BRAM in a MicroBlaze project?

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Hi,

 

That should work, LMB and LMB_BRAM controllers are using 32-bit addresses.

However you are using an old version EDK 9.2 (the latest is 13.2 and 13.3 is soon released).

There has been some issues with the C_MASK on the LMB BRAM controllers in the past.

The C_MASK value mask away all address bits that isn't needed for the address decoding logic.

The values is calculated by the tools and for some systems in the past, it has generated a wrong value.

 

Could you give the C_MASK values from the lmb bram controller wrappers in the /hdl directory?

Could you also attach the complete .mhs file?

 

Göran

 

Adventurer
Adventurer
9,189 Views
Registered: ‎11-13-2008

Re: How to use larger BRAM in a MicroBlaze project?

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Hi Goran,

Here are the C_MASK values for my lmb_bram_if_cntlr controllers:
hdl/dlmb_cntlr_1_wrapper.vhd
  dlmb_cntlr_1 : lmb_bram_if_cntlr
    generic map (
      C_BASEADDR => X"00000000",
      C_HIGHADDR => X"0000FFFF",
      C_MASK => X"c0010000",    <-- Has the same mask as dml_cntlr_2!
      C_LMB_AWIDTH => 32,
      C_LMB_DWIDTH => 32
    )

   ...

hdl/dlmb_cntlr_1_wrapper.vhd:

  dlmb_cntlr_2 : lmb_bram_if_cntlr
    generic map (
      C_BASEADDR => X"00010000",
      C_HIGHADDR => X"00017FFF",
      C_MASK => X"c0010000",
      C_LMB_AWIDTH => 32,
      C_LMB_DWIDTH => 32
    )
   ...
Both controllers have the same mask! It does look like the problem appeared during the Platform Gen step. How can I fix this without changing the tool versions? I am stuck with EDK 9.2 for now due to a Linux kernel I am running on it.

-----
BEFORE I added the second LMB controller, I had the following statement in the system.log:
INFO:MDT - IPNAME:dlmb_cntlr_1 INSTANCE:lmb_bram_if_cntlr -
   /data/Xilinx/9.2i/edk/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v2_10_
   a/data/lmb_bram_if_cntlr_v2_1_0.mpd line 43 - tcl is overriding PARAMETER
   C_MASK value to 0xc0000000

AFTER:
INFO:MDT - IPNAME:dlmb_cntlr_1 INSTANCE:lmb_bram_if_cntlr -
   /data/Xilinx/9.2i_2/edk/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v2_1
   0_a/data/lmb_bram_if_cntlr_v2_1_0.mpd line 43 - tcl is overriding PARAMETER
   C_MASK value to 0xc0010000
INFO:MDT - IPNAME:dlmb_cntlr_2 INSTANCE:lmb_bram_if_cntlr -
   /data/Xilinx/9.2i_2/edk/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v2_1
   0_a/data/lmb_bram_if_cntlr_v2_1_0.mpd line 43 - tcl is overriding PARAMETER
   C_MASK value to 0xc0010000

-----

For MHS with 2 LMB controllers on microblaze_1, see the system.mhs.2lmb_brams file attached to my 09-25-2011 06:06 PM  post.(THIS is the version I am primarily interested in, the 2LMB BRAMs rather than LMB+PLB).
For MHS with 1 LMB and 1 PLB BRAM controller on microblaze_1, see system.mhs.lmb_and_plb_brams file attached to this post (the code snippet in my previous post is from here).

Thanks,

Victor

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Xilinx Employee
Xilinx Employee
9,176 Views
Registered: ‎08-06-2007

Re: How to use larger BRAM in a MicroBlaze project?

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Hi,

 

The MASK tells which address bits are needed to distinquish LMB from PLB and also among LMB slaves if they are multiple on the same LMB bus.

So multiple LMB controllers can have the same MASK.

 

Didn't know that you had multiple MicroBlazes.

Are you sure that you have connected XMD to the 2nd MicroBlaze and not the 1st MicroBlaze?

The 1st MicroBlaze only has 8kbyte of LMB and it will wrap around the addresses you shown from XMD.

 

Next step is to have a simple assembler program that writes and reads to these addresses and simulate it.

In the waveform, you will be able to see what the issue is.

 

Göran

Adventurer
Adventurer
9,173 Views
Registered: ‎11-13-2008

Re: How to use larger BRAM in a MicroBlaze project?

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Goran,

 

 

I doble checked to make sure I do not connect to the wrong microblaze from XMD. microblaze_0 with 8K wraps around 64K (confirmed), the microblaze_1 also wraps around 64K instead of reading further. HOWEVER, read below (I can access 64K+ if synthesized from within ISE!)

 

1) PROJECT 1: EDK 2 contiguous LMB, synthezied from within EDK (As described in the previous posts)

XMD% state

------------------------------------------------

System(0 ) - Hardware System on FPGA(Device 5) Targets:

------------------------------------------------

                Target(0) - MicroBlaze(1) Debug Target

                Target(1) - MDM Uart Channel Target

                Target(2) - MicroBlaze(2) Debug Target*

 

XMD% mrd 0 3

       0:   B8080050

       4:   00000000

       8:   B8080C40

XMD% mrd 0x10000 3

   10000:   B8080050  

   10004:   00000000

   10008:   B8080C40

 

XMD% mwr 0x0 0x23456789

XMD% mrd 0 3

       0:   23456789

       4:   00000000

       8:   B8080C40

XMD% mrd 0x10000 3

   10000:   23456789   <-- wrap around after 64K (not expected)

   10004:   00000000

   10008:   B8080C40

 

----------

2) PROJECT 2: As a part of another project (run on a different machine with supposedly the same tool versions ), the described EDK project is further encapsulated with a wrapper in ISE, with clock manager moved to the top level (that's it for hardware changes at EDK level). Similarly, there are 2 contiguous LMB slaving off the microblaze_1's bus. IN THIS CASE I CAN SEE all 96K in XMD!

 

Can it make a difference like that?

 

--------------------------------------------------------

System(0) - Hardware System on FPGA(Device 5) Targets:

--------------------------------------------------------

Stopped                               Target(0) - MicroBlaze(1) Debug Target

Stopped                               Target(2) - MicroBlaze(2) Debug Target*

 

XMD% mrd 0 3

       0:   B8080050

       4:   00000000

       8:   B8081584

 

XMD% mrd 0x10000 3

   10000:   00000000

   10004:   00000000

   10008:   00000000

 

XMD% mwr 0x10000 0x34343434

XMD% mrd 0x10000 3

   10000:   34343434    <-- Successfully written at 64K

   10004:   00000000

   10008:   00000000

 

XMD% mrd 0 3

       0:   B8080050    <-- 0x0 is still the same

       4:   00000000

       8:   B8081584

 

----------

3) For ISE+EDK, From 96K it wraps to 64K in debugger. It sounds as this is expected.

 

target 2                  

XMD% mrd 0 3

       0:   B8080050

       4:   00000000

       8:   B8081584

                  

XMD% mrd 0x10000 3

   10000:   34343434

   10004:   00000000

   10008:   00000000

 

XMD% mrd 0x18000 3

   18000:   34343434  <-- wrap around after 96K back to 64K

   18004:   00000000

   18008:   00000000

  

----------

4) I did not check whether resynthesizing the same EDK PROJECT #1 on another machine makes a difference yet, but will do.

 

Thanks,

Victor

 

 

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Xilinx Employee
Xilinx Employee
9,157 Views
Registered: ‎08-06-2007

Re: How to use larger BRAM in a MicroBlaze project?

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Hi,

 

That is very weird.

I have never experienced something like this.

 

Have you done "clean hardware" on all these projects before reimplement them?

Sometimes stuff might be left over which maybe a causing this.

 

Next step would be to create to identical projects but one implemented in ISE and compare the EDK directories, especially the /hdl directory.

 

Göran

Adventurer
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9,132 Views
Registered: ‎11-13-2008

Re: How to use larger BRAM in a MicroBlaze project?

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Goran,

 

Good news!

1) After resynthesizing the hardware the problem is gone.

2) I double checked on the other mentioned machine as well with just the EDK without the top wrapper and it also worked.

 

So, it must have been some baggage from the previous HW generation. The only other reason I could think of is if I somehow still used the old bitstream, but I always try to check the timestams, so the former is more likely.

 

To confirm, it is 2 LMB controllers (64K + 32K) connected to the same shared LMB bus that works. I haven't tested the LMB + PLB BRAM option, but it likely didn't work for to the same reason.

 

Thank you for your support,

Victor

 

 

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Explorer
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Re: How to use larger BRAM in a MicroBlaze project?

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Yes, I have wasted hours, days, weeks due to EDK/ISE not rebuilding things that have been updated or should be rebuilt. I have learned to clean hardware everytime I change something of importance otherwise I cannot trust that the tools will rebuild it.

 

I typically work with ISE designs that have and EDK project as a source file. I almost always manually build the netlist in EDK, then clean everything in ISE and then rebuild in ISE in order to get ISE to rebuild the EDK project - otherwise I do not know if I am testing my changed design or the old one.

 

It is too bad I cannot trust the tools to know because it takes longer to build after a clean, but I have experienced this over and over, especially with EDK designs. I am not sure that ISE with an EDK source file is designed to recognize updates in the EDK project - I certainly have not experienced it knowing.

 

Sometimes I will manully go and delete the ISE or EDK implememntation file for the sources that I updated to ensure it will rebuild them. Sometimes this causes me errors so I clean all and start over.

 

Also, often, just opening EDK will cause me to have to rebuild my ISE design or it gives me software errors when trying to buid my software code into the bitstream. This makes no sense to me - especially when ISE rarely recognizes a hardware change in EDK that I want it to see, but it thinks there has been a change when there has not.

 

Clean always if you want to be sure.

 

Hope this helps someone.

 

Josh



Xilinx Employee
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Registered: ‎02-01-2008

Re: How to use larger BRAM in a MicroBlaze project?

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EDK will cache generated netlists for cores. If the netlist is already present, EDK will just copy the cached version instead of re-synthesising. If you have a custom core, it would be nice if EDK re-synthesised if you modified the HDL for the core. Well this is possible.

 

For the custom core, edit the mpd file and add or modify it to contain the following line:

 

OPTION ARCH_SUPPORT_MAP = (others = DEVELOPMENT)

 

With the above line in the mpd of the core, EDK will add all the hdl for that core into the automatically generated system_include.make causing the core to re-synthesis anytime any of its hdl changes.

 

Refer to UG642 for a description of this option in the mpd file.

 

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Explorer
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Re: How to use larger BRAM in a MicroBlaze project?

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Ah yes, I have used OPTION ARCH_SUPPORT_MAP = (others = DEVELOPMENT). I found that very useful except that it rebuilds everytime when really I just want it to rebuild when it has changed. I undertsand the nature of cores and I think this actually operates appropriately.

 

My issue is not that EDK does not rebuild my custom pcore it is that ISE does not rebuild my EDK project even when it has changed and even when I have rebuilt the netlist in EDK. ISE caches the EDK project netlist and does not update it unless I manually delete the EDK cached files in the ISE directory or use 'cleanup project files' to delete everything.

 

FYI, I am using an EDK project as a source file in an ISE project.

 

It appears to me that sometimes ISE knows that the EDK project has changed and says it is out of date, but the majority of the time it is not aware of the EDK project changes. The behavior does not seem consistent or I would not have a problem.

 

To cover myself I assume that it is completely unaware and I clean and rebuild in EDK, then clean and rebuild in ISE to ensure that the modifications propogate through the pipeline of tools.

 

I appreciate your response.

 

Thank you,

Josh

 

 


@johnmcd wrote:

EDK will cache generated netlists for cores. If the netlist is already present, EDK will just copy the cached version instead of re-synthesising. If you have a custom core, it would be nice if EDK re-synthesised if you modified the HDL for the core. Well this is possible.

 

For the custom core, edit the mpd file and add or modify it to contain the following line:

 

OPTION ARCH_SUPPORT_MAP = (others = DEVELOPMENT)

 

 


 

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Explorer
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Re: How to use larger BRAM in a MicroBlaze project?

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It appears that SDK finally no longer fails the elfcheck when concatenating BRAMs, yay!

 

I could be mistaken, but my project builds fine using the methods described in this thread spanning multiple adjacent BRAM memory blocks.

 

Thank you Xilinx!

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Visitor roketroket
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Re: How to use larger BRAM in a MicroBlaze project?

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Hi,

in my microblaze system, i have a 64 KB BRAM and 2 controllers for it (data and instruction), due to the code size, i added one more BRAM with one (instruction) controller and connected it to microblaze i_lmb_controller bus, but it didn't work.

XPS succesfully generated the netlist, then in ISE, i have succcessfully made place and route, but in generating programming file, i received errors saying ;

 

not all bitLanes in address space.

 

Then, i added one more controller for this new BRAM and connect it to the microblaze_d_lmb bus, but for this case in mapping design process in ise, i received an error saying,


BRAM_controller_1_BRAM_PORT_address<<0>> is not finished, it isn't driven by any source.

.

.

.

BRAM_controller_1_BRAM_PORT_address<<31>> is not finished, it isn't driven by any source.

 

except for address pins 15 through 29.

 

 

Any ideas?


 

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Xilinx Employee
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Re: How to use larger BRAM in a MicroBlaze project?

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Hi,

 

Can you share the .mhs file?

It's hard to tell what is wrong without more information.

Have you checked the linker script so it's updated with your extended LMB address range?

 

Göran

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Visitor roketroket
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Re: How to use larger BRAM in a MicroBlaze project?

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Hi Goran,

first of all i m using ISE tools 14.1..

 

the following is my mhs file:

 


# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 14.1 Build EDK_P.15xf
# Tue May 29 16:10:28 2012
# Target Board: Custom
# Family: spartan6
# Device: xc6slx45t
# Package: fgg484
# Speed Grade: -3
# ##############################################################################
PARAMETER VERSION = 2.1.0


PORT RESET = RESET, DIR = I, SIGIS = RST, RST_POLARITY = 1
PORT LEDS_TRI_O = LEDS_TRI_O, DIR = O, VEC = [0:7]
PORT sys_clk_pin = CLK_S, CLK_FREQ = 66000000, DIR = I, SIGIS = CLK


BEGIN proc_sys_reset
PARAMETER INSTANCE = proc_sys_reset_0
PARAMETER HW_VER = 3.00.a
PARAMETER C_EXT_RESET_HIGH = 1
PORT MB_Debug_Sys_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst
PORT Dcm_locked = proc_sys_reset_0_Dcm_locked
PORT MB_Reset = proc_sys_reset_0_MB_Reset
PORT Slowest_sync_clk = clk_132_0000MHz
PORT Interconnect_aresetn = proc_sys_reset_0_Interconnect_aresetn
PORT Ext_Reset_In = RESET
PORT BUS_STRUCT_RESET = proc_sys_reset_0_BUS_STRUCT_RESET
END

BEGIN lmb_v10
PARAMETER INSTANCE = microblaze_0_ilmb
PARAMETER HW_VER = 2.00.b
PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
PORT LMB_CLK = clk_132_0000MHz
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = microblaze_0_i_bram_ctrl
PARAMETER HW_VER = 3.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x0000ffff
BUS_INTERFACE BRAM_PORT = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block
BUS_INTERFACE SLMB = microblaze_0_ilmb
END

BEGIN lmb_v10
PARAMETER INSTANCE = microblaze_0_dlmb
PARAMETER HW_VER = 2.00.b
PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
PORT LMB_CLK = clk_132_0000MHz
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = microblaze_0_d_bram_ctrl
PARAMETER HW_VER = 3.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x0000ffff
BUS_INTERFACE SLMB = microblaze_0_dlmb
BUS_INTERFACE BRAM_PORT = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block
END

BEGIN bram_block
PARAMETER INSTANCE = microblaze_0_bram_block
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block
BUS_INTERFACE PORTB = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block
END

BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER HW_VER = 8.30.a
PARAMETER C_INTERCONNECT = 2
PARAMETER C_USE_BARREL = 1
PARAMETER C_USE_FPU = 1
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_ICACHE_BASEADDR = 0xa0a10000
PARAMETER C_ICACHE_HIGHADDR = 0xa0a1ffff
PARAMETER C_USE_ICACHE = 1
PARAMETER C_CACHE_BYTE_SIZE = 8192
PARAMETER C_ICACHE_ALWAYS_USED = 1
PARAMETER C_DCACHE_BASEADDR = 0xa0a10000
PARAMETER C_DCACHE_HIGHADDR = 0xa0a1ffff
PARAMETER C_USE_DCACHE = 1
PARAMETER C_DCACHE_BYTE_SIZE = 8192
PARAMETER C_DCACHE_ALWAYS_USED = 1
PARAMETER C_USE_DIV = 1
BUS_INTERFACE M_AXI_DP = axi4lite_0
BUS_INTERFACE M_AXI_DC = axi4lite_0
BUS_INTERFACE DEBUG = microblaze_0_debug
BUS_INTERFACE DLMB = microblaze_0_dlmb
BUS_INTERFACE ILMB = microblaze_0_ilmb
BUS_INTERFACE M_AXI_IC = axi4lite_0
PORT MB_RESET = proc_sys_reset_0_MB_Reset
PORT CLK = clk_132_0000MHz
END

BEGIN mdm
PARAMETER INSTANCE = debug_module
PARAMETER HW_VER = 2.00.b
PARAMETER C_INTERCONNECT = 2
PARAMETER C_USE_UART = 1
PARAMETER C_BASEADDR = 0x41400000
PARAMETER C_HIGHADDR = 0x4140ffff
BUS_INTERFACE S_AXI = axi4lite_0
BUS_INTERFACE MBDEBUG_0 = microblaze_0_debug
PORT Debug_SYS_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst
PORT S_AXI_ACLK = clk_132_0000MHz
END

BEGIN clock_generator
PARAMETER INSTANCE = clock_generator_0
PARAMETER HW_VER = 4.03.a
PARAMETER C_CLKIN_FREQ = 66000000
PARAMETER C_CLKOUT0_FREQ = 132000000
PARAMETER C_CLKOUT0_GROUP = NONE
PARAMETER C_CLKOUT0_BUF = TRUE
PARAMETER C_CLKOUT0_DUTY_CYCLE = 0.500000
PARAMETER C_CLKOUT0_PHASE = 0
PORT LOCKED = proc_sys_reset_0_Dcm_locked
PORT CLKOUT0 = clk_132_0000MHz
PORT RST = RESET
PORT CLKIN = CLK_S
END

BEGIN bram_block
PARAMETER INSTANCE = axi_bram_ctrl_0_bram_block
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = axi_bram_ctrl_0_bram_porta_2_axi_bram_ctrl_0_bram_block_porta
BUS_INTERFACE PORTB = axi_bram_ctrl_0_bram_portb_2_axi_bram_ctrl_0_bram_block_portb
END

BEGIN axi_bram_ctrl
PARAMETER INSTANCE = axi_bram_ctrl_0
PARAMETER HW_VER = 1.03.a
PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 8
PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 8
PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 8
PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 8
PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 8
PARAMETER C_S_AXI_BASEADDR = 0xa0a10000
PARAMETER C_S_AXI_HIGHADDR = 0xa0a1ffff
BUS_INTERFACE BRAM_PORTA = axi_bram_ctrl_0_bram_porta_2_axi_bram_ctrl_0_bram_block_porta
BUS_INTERFACE BRAM_PORTB = axi_bram_ctrl_0_bram_portb_2_axi_bram_ctrl_0_bram_block_portb
BUS_INTERFACE S_AXI = axi4lite_0
PORT S_AXI_ACLK = clk_132_0000MHz
END

BEGIN axi_interconnect
PARAMETER INSTANCE = axi4lite_0
PARAMETER HW_VER = 1.06.a
PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0
PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn
PORT INTERCONNECT_ACLK = clk_132_0000MHz
END

BEGIN axi_gpio
PARAMETER INSTANCE = LEDS
PARAMETER HW_VER = 1.01.b
PARAMETER C_GPIO_WIDTH = 8
PARAMETER C_ALL_INPUTS = 0
PARAMETER C_INTERRUPT_PRESENT = 0
PARAMETER C_IS_DUAL = 0
PARAMETER C_BASEADDR = 0x40000000
PARAMETER C_HIGHADDR = 0x4000ffff
BUS_INTERFACE S_AXI = axi4lite_0
PORT S_AXI_ACLK = clk_132_0000MHz
PORT GPIO_IO_O = LEDS_TRI_O
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = bram_cntlr_0
PARAMETER HW_VER = 3.00.b
PARAMETER C_BASEADDR = 0x00010000
PARAMETER C_HIGHADDR = 0x0001ffff
BUS_INTERFACE BRAM_PORT = bram_cntlr_0_BRAM_PORT
BUS_INTERFACE SLMB = microblaze_0_ilmb
END

BEGIN bram_block
PARAMETER INSTANCE = bram_block_0
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = bram_cntlr_0_BRAM_PORT
END

 

 

 

i also attached the system architecture in the attachments.

 

architecture.png
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Visitor roketroket
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Re: How to use larger BRAM in a MicroBlaze project?

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Also, this is my address map:

 

I'm trying to make the BRAM address space larger because of the software's code size (nearly 100 KB). My FPGA is Spartan 6. I have errors when generating programming file process in ISE. XPS generates netlist correctly and synthesis, translate and par processes success, too.

architecture2.png
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Xilinx Employee
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Re: How to use larger BRAM in a MicroBlaze project?

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Hi,

 

So which error do you get for this .mhs?

 

Göran

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Visitor roketroket
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Re: How to use larger BRAM in a MicroBlaze project?

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Goran, I decided not to use the LMB bus for data and instruction buses (because of the errors above) and used the AXI_DP and AXI_IP interfaces of microblaze for the code and data memory. When i try to create 2 AXI BRAM controllers which have addresses aligned (one ends @ 0x10000FFF, another starts @ 0x10001000), i generate programming file succesfully, i check the .ld file and it's correct, but as u know the SDK doesn't allow us to use these 2 BRAMS for the .text area even if we edit the .ld source manually. (It gives the error that the address range of the first memory isn't in the range). I think EDK allows this but we have no longer EDK. So how can i handle a .text of size bigger than 64 KB?

 

Thanks a lot.

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Visitor roketroket
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Re: How to use larger BRAM in a MicroBlaze project?

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I receive following error :



ERROR:PhysDesignRules:368 - The signal
<cpu_i/bram_cntlr_0_BRAM_PORT_BRAM_Addr<30>> is incomplete. The signal is not
driven by any source pin in the design.
ERROR:PhysDesignRules:368 - The signal
<cpu_i/bram_cntlr_0_BRAM_PORT_BRAM_Addr<31>> is incomplete. The signal is not
driven by any source pin in the design.
ERROR:Bitgen:25 - DRC detected 2 errors and 21 warnings. Please see the
previously displayed individual error or warning messages for more details.
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Xilinx Employee
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Re: How to use larger BRAM in a MicroBlaze project?

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Hi,

 

This errors doesn't make sense at all.

Have you tried to clean the hardware implementation files and rebuild the design?

 

Göran

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Re: How to use larger BRAM in a MicroBlaze project?

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I recently received the same if not a very similar error using v13.4 tools.

 

I really do not know what the problem was, but it magically fixed itself. (perhaps by cleaning  the project files as suggested above)

 

I have had numerous issues due to not cleaning. I expect the tools to figure it out, butthey are not as aware as they could be. I have also had a lot of EDK issues recently ( in v13.4) where things stop working and I recreate the project and paste in the old MHS file and everything works perfectly again. Somehow my projects have been getting corrupted or something and/or things go awry even wihtout any changes to any source files.

 

I am shocked that the tools will not make larger BRAMs automatically. Users should not have to trick the tools to do something so basic and seemingly widely used.

Why add so many BRAMs and make it a pain in the butt to use more than a tiny amount in an embedded project?

 

I would suggest cleaning the ISE project files and the EDK project (warning 'clean hardware' deletes your SDK directory if you have any files in EDK/SDK - really really not cool at all). The rebuild EDK then ISE and see if you get the same error.

 

Josh

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