I am trying to write a testbench for I2S transceiver but I have couple of questions. This is my second design and my questions might be so basic.
In this design my FPGA is the slave and the Audio Codec will be the master. I am using Xilinx I2S receiver and transmitter IPs. I modified the IP properties of both receiver and transmitter to act as Slave ( IS_Master = 0 ) then I added receiver and transmitter to my i2s_top ( transceiver ) and added some extra logic so the data line knows if it receives the data or sending the data. Now I need to write a testbench for it.
entity i2s_top is Port ( clk : in std_logic; rst : in std_logic; en_rx_tx : in std_logic; -- Enable : 0 (RX) , Enable : 1 (TX) i2s_mclk : in std_logic; -- 256 * sampling rate of data converter i2s_sck : in std_logic; i2s_ws : in std_logic; i2s_sd0 : inout std_logic -- Data bus ); end i2s_top;
In my testbench I have i2s_top as a component, then I have instantiated the DUT (i2s_top) then I have 4 processes for system clk, MClk, Sck and WS.
My main issue is in the process for stimuli . While I was reading about the i2s interface, and when I checked i2s receiver example design, I believe I need to use tvalid , tready, tdata signals but those signals are in the sub-modules of i2s_top so they are not in my testbench. ( Please correct me if I am wrong )
I googled and found how to add signals from submodules to top testbench:
signal i2s_receiver_codec.m_axis_aud_tready_0 : std_logic;
but it seems like this is not a right way to use the signals from sub modules. (I am getting syntax error)
My second question is should I write seperate testbenches for TX and RX eventhough they are sub-modules of the i2s_top(transceiver) ?
my other question is do we have anything similar to $random in verilog in VHDL ?
Is there any examples that I can follow with the same structure as I2S ? I am so confused!