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Observer rforsyth
Observer
7,420 Views
Registered: ‎03-25-2013

IDELAYCTRL instantiation for xps_II_temac Hard Ethernet MAC core - Virtex 4

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Hello - I am working on a legacy Virtex 4 XPS design and porting it to new hardware - the target is the xc4vfx60ff672-10

 

The pcb was designed so that all clocks now come in through Global clock pins, as they  did not in the legacy design.

With the new pin configuratoin I am getting this error when generating the bit file in XPS implying that I need to intantiate an IODELAY delay controller.

 

 

ERROR:Place:872 - Delay element
   "Hard_Ethernet_MAC/Hard_Ethernet_MAC/V4HARD_SYS.I_TEMAC/SINGLE_GMII.I_EMAC_TO

P/gmii_rx_clk_delay_0_i" has been placed at ILOGIC_X1Y167 due to the
   following location constraint on component "temac_GMII_RX_CLK_0_pin":
    COMP "temac_GMII_RX_CLK_0_pin" LOCATE =  SITE "C14" LEVEL 1
   However, the delay controller that calibrates this delay element has not been
   used. Please instantiate a delay controller and apply appropriate location
   constraint, or instantiate one delay controller for the design with out any
   location constraint. Please refer to the usage document to use the controller
   efficiently.

 

From reading the temac user guide it seems to me that these lements are instantiated automatically by the IP config GUI.

 

I see these parameters in the mhs fole for the xps_ll_temac:

 

PARAMETER C_NUM_IDELAYCTRL = 2
 PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X1Y5-IDELAYCTRL_X1Y5

 

From PLanahead I found the clock region for these GC pins to be X0Y5 and the associated IDELAYCTRL to be IDELAYCTRL_X1Y5

 

I still get the error.

 

I even tried manually instantiating in the xps_ll_temac.vhd wrapper, adding the following:

 

dlyctrl_1:IDELAYCTRL
port map(
RDY => rdy _1,
REFCLK => REFCLK,
RST => rst_1
);
--
attribute loc of dlyctrl_1 is IDELAYCTRL_X1Y5;

 

I still get the error.

 

Can anyonie tell me where and how to instantiate the IDELAYCTRL

 

I've searched the Virtex4 User guide, and the LogiCore IP XPS LL TEMAC data sheet which give instantiation templates, but no clarity as to where the instantiation is done and no example.

 

Thank you!

 

 

 

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Observer rforsyth
Observer
13,723 Views
Registered: ‎03-25-2013

Re: IDELAYCTRL instantiation for xps_II_temac Hard Ethernet MAC core - Virtex 4

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Hi thanks for the responses and info.
I found that the temac core does the instantiation automatically, but I had to tell it physically where the new IDELAYCTRL elements are located on the die using Planahead to locate the IDELAYCTRL elements on the die. - then went back into the configure IP GUI (or the mhs file) and set the C_NUM_IDELAYCTRL to 3 (for my case) and C_IDELAYCTRL LOC = IDELAYCTRL_X0Y7-IDELAYCTRL_X0Y6_IDELAYCTRL_X1Y5 (determined by my pinout for the temac signals).

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3 Replies
Xilinx Employee
Xilinx Employee
7,114 Views
Registered: ‎09-20-2012

Re: IDELAYCTRL instantiation for xps_II_temac Hard Ethernet MAC core - Virtex 4

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Hi @rforsyth

 

Try locking it to X0Y5 site.

 

dlyctrl_1:IDELAYCTRL
port map(
RDY => rdy _1,
REFCLK => REFCLK,
RST => rst_1
);
--
attribute loc of dlyctrl_1 is IDELAYCTRL_X0Y5;

 

 

Thanks,

Deepika.

Thanks,
Deepika.
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Xilinx Employee
Xilinx Employee
7,106 Views
Registered: ‎08-02-2007

Re: IDELAYCTRL instantiation for xps_II_temac Hard Ethernet MAC core - Virtex 4

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hi

 

depending on the temac configuration there are a few recommendations relating to MHS and UCF.

http://www.xilinx.com/support/answers/32713.html

 

--hs

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Observer rforsyth
Observer
13,724 Views
Registered: ‎03-25-2013

Re: IDELAYCTRL instantiation for xps_II_temac Hard Ethernet MAC core - Virtex 4

Jump to solution
Hi thanks for the responses and info.
I found that the temac core does the instantiation automatically, but I had to tell it physically where the new IDELAYCTRL elements are located on the die using Planahead to locate the IDELAYCTRL elements on the die. - then went back into the configure IP GUI (or the mhs file) and set the C_NUM_IDELAYCTRL to 3 (for my case) and C_IDELAYCTRL LOC = IDELAYCTRL_X0Y7-IDELAYCTRL_X0Y6_IDELAYCTRL_X1Y5 (determined by my pinout for the temac signals).

View solution in original post

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