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3,659 Views
Registered: ‎06-21-2017

INT_ID

I am running on an UltraZed board and trying to set up an interrupt driven function.  I configured the ZU1 to have a PL to PS interrupt as shown.

int0.jpg

 

A pl_ps_irq0(0:0) port appeared on my Zynq block and I connected it to something in my fabric.  I built the design and exported to SDK.  My question is simple, which of the Interrupt-IDs in the xparameters_ps.h file corresponds to this interrupt?

 

Thanks

Bruce

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11 Replies
Visitor
Visitor
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Registered: ‎11-24-2015

Re: INT_ID

I generally find these in the xparameters.h file instead of the xparameters_ps.h file. Do a search within the file for "INTR" which should locate them
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3,635 Views
Registered: ‎06-21-2017

Re: INT_ID

I don't see any INTR strings in the xparameters.h file.  There are a bunch in the xparameters_ps.h file.  Some are obviously not the one I'm looking for.  It's easy to rule out the ones with UART, I2C or SPI in the name. 

 

Disclaimer:  I'm just a poor hardware weenie who's boss left town before he assigned a software engineer to this job.  My version of Kernighan and Richie is copyright 1988.  It's been a while.

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Xilinx Employee
Xilinx Employee
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Registered: ‎04-15-2011

Re: INT_ID

Hi, Bruce,

 

Please make sure this interrupt pin is connecting to a existing IP. For example, if the interrupt from axi_timer is connected to PL_PS_irq[0], you should see the XPAR_FABRIC_AXI_TIMER_0_INTERRUPT_INTR in xparameters.h, which defines the interrupt ID.

 

/* Definitions for Fabric interrupts connected to psu_acpu_gic */
#define XPAR_FABRIC_AXI_TIMER_0_INTERRUPT_INTR 121

 

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Highlighted
3,589 Views
Registered: ‎06-21-2017

Re: INT_ID

 
Thanks for the reply.  My interrupt is tapped off of a bus coming out of some custom VHDL as shown.  The VHDL, in fact the whole scheme, works in the non-interrupt driven version.  An interesting thing that I noticed is that while I see a new file date on the  xparameters_ps.h when I build new fabric and export to SDK, I haven't seen a new date on the xparameters.h file for a while (8/23 to be exact). 
 
Int.jpg
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Xilinx Employee
Xilinx Employee
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Registered: ‎04-15-2011

Re: INT_ID

I think the reason is that you don't set interrupt type to the port that is connected to pl_ps_irq.

If you add a new port in your block design, you can select different types(i.e. clock, interrupt, reset, etc.) of the port. I am not sure if there is a easy way to add the interrupt type of the port in your VHDL module. But you can do this by package your module as a IP. 

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3,385 Views
Registered: ‎06-21-2017

Re: INT_ID

You're probably correct that I need to set the port type to "INTR".  I am having a dickens of a time making this happen.  I changed my VHDL to have the interrupt come out on a separate pin of the addr_gen_0 block.  The pin property defaulted to undef and is read only in the properties window.  I tried adding an interrupt port to the addr_gen_0 and letting Vivado connect the port to the Int_Out pin on the addr_gen_0 block.  Vivado changed the pin to interrupt but it created an interface out of the block diagram.  When I connected the to the interrupt input on the Zynq PS, the pin changed back to undefined. 

 

The language template has an example of how to define an interrupt port.  I copied this into my code and filled in the <interrput_port_name> like so:

 

entity addr_gen is
Port (
   Clock          : in std_logic;
   Dvalid         : in std_logic;
   InputControl   : in std_logic_vector(31 downto 0);
   Run            : in std_logic_vector(31 downto 0);

   OutputWord     : out std_logic_vector(31 downto 0);
   Count_Out      : out std_logic_vector(31 downto 0);
   wea            : out std_logic_vector(3 downto 0);
   Int_Out        : out std_logic;
   addr_out       : out std_logic_vector(31 downto 0)
);
END addr_gen;

Architecture RTL of addr_gen is

Constant zeros            : std_logic_vector(30 downto 0) := "0000000000000000000000000000000";

signal count              : unsigned(31 downto 0) := (OTHERS => '0');  --
signal ValidPipe          : std_logic_vector(7 downto 0) := (OTHERS => '0');  --
signal bit11              : std_logic  := '0';
signal ack                : std_logic;
signal BufFlag            : std_logic := '0';

-- Declare the attributes in the architecture section
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO of Int_Out: SIGNAL is "xilinx.com:signal:interrupt:1.0 Int_Out INTR";
-- Supported parameter: SENSITIVITY { LEVEL_HIGH, LEVEL_LOW, EDGE_RISING, EDGE_FALLING }
-- Normally LEVEL_HIGH is assumed.  Use this parameter to force the level
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER of Int_Out: SIGNAL is "LEVEL_HIGH";

 

I have the following errors & critical warnings:

 

  • [IP_Flow 19-1789] Bus Interface 'Int_Out': Bus interface "Int_Out" does not contain any port map.
  • [BD 41-134] No portmaps are present on the interface: Int_Out
  • [IP_Flow 19-4777] Ignore unrecognized attribute X_INTERFACE_PARAMETER 'LEVEL_HIGH'.
  • [Coretcl 2-1280] The upgrade of 'design_1_addr_gen_0_0' has identified issues that may require user intervention. Please verify that the instance is correctly configured, and review any upgrade messages.

So what did I do wrong?

 

 

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3,226 Views
Registered: ‎06-21-2017

Re: INT_ID

There is a typographical error in the VHDL language template for the interrupt attribute.  See https://forums.xilinx.com/t5/Design-Entry/Interrupt-Attribute/td-p/798715.

 

After correcting the error, the pin on my RTL block is of type "intr".  I connected this pin to the pl_ps_irq of the Zynq block, generated a bit stream, exported the hardware and tried to rebuild the project in SDK. There are still a few coding errors in my c file, but it's kind of hard to write decent code using an interrupt if you can't find the interrupt. 

 

Still no new interrupts showing up in the xparameters.h file.  In fact, the only occurrences of "INTERRUPT"  in that file are in definitions for the GPIOs left over from the example I started with.  So what gives?  I connected an interrupt pin output from my VHDL to an irq input on the Zynq.  Why doesn't Vivado/SDK see it?

 

 

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Xilinx Employee
Xilinx Employee
3,208 Views
Registered: ‎04-15-2011

Re: INT_ID

Hello,

 

I have a quick test, but don't replicate your issue on my end. 

I use your templates and connect it like below picture. Then I can see interrupt ID in xparameters.h

I've attched my VHDL code. You can try it on your end.

interrupt_0.PNG

interrupt_1.PNG

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3,198 Views
Registered: ‎06-21-2017

Re: INT_ID

 
No luck.  I commented out the interrupt attributes in the code I had generating the interrupt request, then ran the irq through your code as shown:
 
int2.jpg
 
I rebuilt the project (generated bit stream), exported hardware to SDK, and rebuilt my SDK project.  Still no fabric interrupts in xparameters.h.  What steps am I missing?  I have a non-interrupt driven version of the same project that works just fine. 
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Xilinx Employee
Xilinx Employee
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Registered: ‎04-15-2011

Re: INT_ID

bruce_karaffa

I am not sure why it doesn't work for you. What's the Vivado version you are using? You could create a new test project and connect my RTL module like what I've done in previous post, then check if you could see the interrupt ID.
As a tip, you don't have to generate bitstream to check this. You could generate block design then export HDF without bitstream, then generate a new BSP in SDK and check xparameters.h.
If you still don't see this, upload your HDF file, I'd like to check your HDF file.

-Longley
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1,456 Views
Registered: ‎06-21-2017

Re: INT_ID

I am using Vivado 2017.2.  My system.hdf file is attached.  I may have been missing the step of regenerating the BSP.  I tried this time.  I tried to add the xilfpga libraries since that looks like something I might need.  This didn't work, as it couldn't delete the old folder.  I gave authorized users full control and regenerated the BSP without the xilfpga libraries and it worked.  I then tried with the xilfpga libraries and got the same problem.  The last couple hundred lines of my SDK log file are also posted.  Still no interrupts in xparameters.h (attached) except for the GPIO interrupts present in the example project.

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