UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Observer cmuhlbauer
Observer
716 Views
Registered: ‎02-14-2018

IOP_SWITCH clock

In UG1085, Zynq UltraScale+ Device TRM, page 1044, the IOP_SWITCH_CLK is referenced as the clock source for the MDC signal.  In Vivado (v2018.1), an IOU_SWITCH clock is setup in "Clock Configuration" but there is no IOP_SWITCH_CLK.  Also, in UG1085, the IOU_SWITCH clock is also referenced in two places.  I suspect these are referring to the same clock.  Please confirm these are the same clock or let me know how to setup the IOP_SWITCH clock.

0 Kudos
1 Reply
Moderator
Moderator
665 Views
Registered: ‎07-31-2012

Re: IOP_SWITCH clock

Hi @cmuhlbauer,

 

GEM clock source is IOPLL in general when configured in PS.

IOPLL in LPD are interconnect and switch clock source for IOPLL.

 

Yes, it is IOU_SWITCH clock.

 

Regards

Praveen


-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos