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Visitor asicguy
Visitor
2,048 Views
Registered: ‎05-17-2013

IP Packager and tri-states

I am trying to package up some IP from the EDK so I can use it in IP Integrator. When I import it looks like only the verilog and vhdl files are analyzed and all I see on the block diagram are the *_I, *_O, and *_T signals.

 

When I look at some prepackaged IP, such as the axi_gpio, I see that the core has a bidirectional signal "GPIO". How can I create a bidirectional signal in my IP?

 

Thanks!

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Xilinx Employee
Xilinx Employee
2,035 Views
Registered: ‎08-02-2011

Re: IP Packager and tri-states

Have you tried declaring the port as type 'inout'

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