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Explorer
Explorer
4,331 Views
Registered: ‎08-26-2014

Implemented two different IPs using 32 and 64 AXI Master buses but transfer speed does not change

Hello,

 

I am testing short data transfer speeds with a Vivado HLS-generated IP using the AXI Master.

 

It justs simply reads 6 32-bit integers or 3 64-bit integers from the input and writes them back to the output. Here the simple C code used for the 32-bit version:

 

int ddr_test(volatile int *inaddr, volatile int *outaddr)
{
#pragma HLS INTERFACE s_axilite port=return bundle=CTRL_BUS
#pragma HLS INTERFACE m_axi depth=6 port=inaddr offset=slave bundle=MASTER_BUS
#pragma HLS INTERFACE m_axi depth=6 port=outaddr offset=slave bundle=MASTER_BUS

	outaddr[0] = inaddr[0];
	outaddr[1] = inaddr[1];
	outaddr[2] = inaddr[2];
	outaddr[3] = inaddr[3];
	outaddr[4] = inaddr[4];
	outaddr[5] = inaddr[5];

	return 0;
}

And here the 64-bit version:

 

int ddr_test(volatile long long *inaddr, volatile long long *outaddr)
{
#pragma HLS INTERFACE s_axilite port=return bundle=CTRL_BUS
#pragma HLS INTERFACE m_axi depth=3 port=inaddr offset=slave bundle=MASTER_BUS
#pragma HLS INTERFACE m_axi depth=3 port=outaddr offset=slave bundle=MASTER_BUS

	outaddr[0] = inaddr[0];
	outaddr[1] = inaddr[1];
	outaddr[2] = inaddr[2];

	return 0;
}

I checked the data width of the generated AXI channels and they are 32- and 64-bits respectively. Also important to note that the latencies for a 4ns clock are 70 and 42 respectively.

 

I then create the hardware using Vivado, set the HP0 port to 64-bit wide bus in both versions (I guess Vivado implements 32 or 64 accordingly) and then in the SDK I call the IP using these lines:

 

XDdr_test_Set_inaddr(&doDdr_test,MEM_BASE_ADDR);
XDdr_test_Set_outaddr(&doDdr_test,MEM_BASE_ADDR+20);

timer.startTimer();
// Start and wait until it's done
XDdr_test_Start(&doDdr_test);
while(!XDdr_test_IsDone(&doDdr_test));
timer.stopTimer();
time = timer.getElapsedTimerInSeconds();
printf("Execution time = %e\n",time);

Why am I getting the same execution times when writing to DDR with both versions (~2.3e-06s) ?

 

Thanks for your help.

 

Cerilet

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4 Replies
Teacher muzaffer
Teacher
4,276 Views
Registered: ‎03-31-2012

Re: Implemented two different IPs using 32 and 64 AXI Master buses but transfer speed does not change

@cerilet I'd say your measurement methodology needs improvement. One single read over a GP port takes roughly 120~160ns and this is the same delay in your 40 to 70 clocks. Also your timer is probably not very high precision either.

If you want to make better measurement, increase the number bytes you copy say to 1K or 4K. Then you will definitely see the difference even with your low precision measurement.

- Please mark the Answer as "Accept as solution" if information provided is helpful.
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Explorer
Explorer
4,265 Views
Registered: ‎08-26-2014

Re: Implemented two different IPs using 32 and 64 AXI Master buses but transfer speed does not change

Hi @muzaffer,

 

My purpose is not measuring the data speed over both channels. My purpose is to measure how long it takes to tranfer those 24 bytes in both directions because my IP needs only that amount of data to work.

 

So rather than measuring the maximum speed of the channel, I want to know what is the fastest way to transfer 24 bytes only.

I actually haven't substracted the 280ns the timer needs to start and stop (measured calling one function after the other). Do you suggest another way of doing it?

 

How to be sure if the transfer is being done using 32- and 64-bit wide transfers?

 

Thanks for your help.

 

Cerilet

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Teacher muzaffer
Teacher
4,255 Views
Registered: ‎03-31-2012

Re: Implemented two different IPs using 32 and 64 AXI Master buses but transfer speed does not change

@cerilet

>> My purpose is to measure how long it takes to transfer those 24 bytes in both directions because my IP needs only that amount of data to work.

 

I usually don't like to question the premise of a question but in this case I am not sure if it's really valid. Can you describe how your IP will be used? Are you sure there are no opportunities to do any batch processing ie wait for multiple requests and transfer all of them in one shot? Is the IP going to be under processor control at all times or is there an external trigger which can tell PL what needs to be done?

 

To check if the transfers are actually 64 bits, you can add an ILA and observe the number of clocks it takes for this to happen and look at the wdata on each side to verify that the sizes you want are enforced.

- Please mark the Answer as "Accept as solution" if information provided is helpful.
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Explorer
Explorer
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Registered: ‎08-26-2014

Re: Implemented two different IPs using 32 and 64 AXI Master buses but transfer speed does not change

No problem about asking anything, @muzaffer.

 

I am implementing a Real-Time Simulator of a system where I have its mathematical model in the PL and the control of the system in the processor. So I need the results of the previous execution to decide what will be the next time step's input signals before calling the IP again.

 

I have included an ILA core to verify the data transfers between PL and PS but I get this error:

 

WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
Resolution: 
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
WARNING: [Labtools 27-1974] Mismatch between the design programmed into the device xc7z020_1 and the probes file(s) D:/Xilinx/Projects/DFIG_AXI_Master_OCM_64bits/DFIG_AXI_Master_OCM.runs/impl_1/debug_nets.ltx.
The device design has 0 ILA core(s) and 0 VIO core(s). The probes file(s) have 1 ILA core(s) and 0 VIO core(s).
Resolution: 
1. Reprogram device with the correct programming file and associated probes file(s) OR
2. Goto device properties and associate the correct probes file(s) with the programming file already programmed in the device.

The User Chain is 1 and the clock used in the ILA is the same as the IP which comes from the Zynq (250MHz).

 

I have also verified the Programming file (design_1_wrapper.bit) and the Probes file (debug_nets.ltx) which are automatically called by Vivado when programming the Zynq.

 

I tried configuring the ILA in either AXI mode and Native but I get the same error. I couldn't find any solution in the forum.

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