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Visitor shev-rg
Visitor
190 Views
Registered: ‎11-07-2018

Incorrect PS DDR read through S_AXI_HP_FPD port

We are implemented our custom IP block that reads data from PS DDR via S_AXI_HP1_FPD port of RFSoC Zynq PS8 subsystem.

Our architecture assumes that test data are stored in PS DDR, CPU software informs TX part of IP block start address and amount of data that should be read and then transmitted.

For debug purposes we fixed start address in DDR, amount of read data and data values that test pattern are selected as linear increased 64-bit words (0xCAFEBABE_00000000, 0xCAFEBABE_00000001, 0xCAFEBABE_00000002 e.t.c.). Address spaces with test data is configured in software as ‘NORM_NONCACHE’ and cache should be disabled for the current DDR area.

According to AXI4 specification IP module reads two data blocks (TB) from DDR in several transactions. All read transactions except the last within one TB are maximum size (ARLEN = 0xFF), the last transaction of TB are less. TB are read in serial one by one. AXI data width is 128 bit (AxSIZE = 0x4).

We faced with the next problem in hardware tests. During read operations we see that sometimes incorrect data is observed on RDATA bus (see screen shot below). These values are looked like read in previous transaction. RDATA_0 are the least 32 bits of 128-bit RDATA. We could see that red marked part of signal is linear but with some offset similar to previous transaction data. It happens only if the previous size wasn’t maximum. All parameters of AXI4 transaction are set correctly. What could be a reason of the such incorrect read data? It looks like that problems could be with FIFO of AXI HP port? But we checked FIFO rcount and racount counters of the HP_FPD port and didn’t find any strange things.

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Visitor shev-rg
Visitor
178 Views
Registered: ‎11-07-2018

Re: Incorrect PS DDR read through S_AXI_HP_FPD port

Besides read we have problems with write data. Our custom IP has loopback between TX and RX and when it is enabled then read data is written to another section of DDR (RX DDR area) and compared with TX.

Problem with data writing is appeared that some 128-bit words aren't wiritten to DDR and we read null values. Location of the null words is fixed for the size of TB but it isn't start or end of write burst.

Interesting fact that problem with data writing is correlated with erros on data reading. If we have incorrect words in read data (as described in the post above) then we will have null words instead corect on RX DDR area.

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