12-17-2018 08:39 AM
I have got External Differential clock (via LVDS), which I would like to connect to MMCM (Clock Wizard) as clock of MMCM. So, I used IBUFDS and then I used BUFG. External Differential Clock frequency is 50MHz and I want generate 200MHz out of it through MMCM. For this reason, I changed the parameter of input clock from 100MHz to 50MHz. However, everytime its returning an error with FREQ_HZ of BUFG is not matching with clock wizard input clock.
Please suggest me what should I do. Thanks in advance.
12-17-2018 09:00 AM
If you wired-up everything and THEN changed the MMCM parameters, the external components (IBUFDS and BUFG) likely took the original FREQ_MHZ attribute of MMCM: 100 MHz. You'll need to update those manually. In the future, either set the MMCM parameters before connecting it to other components, or configure the MMCM to include those components as part of its own instantiation.
12-17-2018 10:21 AM
Most likely your Clocking Wizard configuration is still set to 100MHz.
All you should need to do is to open the Clocking Wizard GUI and set both the new frequency and input mode, as highlighted in the image below:
12-17-2018 01:46 PM
If things are still not working for you then try this:
12-18-2018 03:29 PM
Thanks for everyone's input.
However, still I couldn't resolve the issue. I've attached the screenshot what I am trying to achieve.
After program the device, ILA is not turning up. Its showing the following warning
"WARNING: [Labtools 27-3413] Dropping logic core with cellname:'interface_demo_i/ila_1' at location 'uuid_885AC90C874C5D918040051FD6246F9B' from probes file, since it cannot be found on the programmed device."
Can anyone help me out? Thanks in advance.
12-18-2018 05:15 PM
Where is the reset_1 pin going to? is it assigned to a physical button/switch in your board? Is this button/switch active-high or active-low?
I suspect you are accidentally holding the reset pin up, which is causing the MMCM to be always in reset mode and never deliver the clock to the ILA.
I just create an example design (almost) exactly the same as yours. I assigned the reset to a button on my ZCU102. When I program the board and keep pressing down the reset button (actively reseting the MMCM) I get exactly the same error.
WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped. INFO: [Labtools 27-1434] Device xczu9 (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3361] The debug hub core was not detected. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active. 2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'. For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908). WARNING: [Labtools 27-3413] Dropping logic core with cellname:'design_1_i/ila_0' at location 'uuid_BE177176557E59FEACE2FE04795A2B22' from probes file, since it cannot be found on the programmed device.
When I reprogram the board without pressing down the button, it all works great!
Please check your board and button to see if it's active-high or active-low.
Alternatively, you can open the Clocking Wizard IP and configure the Reset to be active-low instead of active-high. Then re-synthesize, re-implement, re-generate the bistream and try again.
12-18-2018 05:46 PM
Of course, the input clock must be present, too.
If the reset turns out to be ok, and you cannot get an o-scope probe on the clock to verify it's toggling, change the test design so that the ILA is clocked by the direct input clock. You'll have to instantiate the IBUF's and BUFG, external to the MMCM. If you get the same error, then the input clock is not toggling.
12-19-2018 07:07 AM
I often use a combination of the startup block and the chipscope VIO core. Connecting VIO to your clks are resets gives you activity and level indications of your signals. And by instantiating the startup block in your design, you can use the config clk which originates from a ring osc in the config logic so that clk is always available.
I've attached the verilog, for the startup block, that I add to IPI as a module. In case you haven't used IPI modules, add the .v as source to the project, then in IPI, right click->add_module and select startup
Since you mention FREQ_HZ, that is a property that is propagated through IPI and used to assign frequency values. Instead of using your own BUFG, use 'utility buffer' and set it to BUFG. This IP will propigate the parameter FREQ_HZ from its input to output.
You haven't shared your block diag so here's my take on what you are doing. Also, notice that my import ports have a frequency assigned to them.