cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
7,510 Views
Registered: ‎06-02-2016

Interfacing an 3 Gsps ADC ADC08D1520 at 750Mhz

Hi All,

 

I'm trying to get an TI ADC08D1520 running at 3GSPS (8 bits per sample) connected to a ZYNQ7020 devices. The idea is to log the data to external DDR memory. But the more I work on this the more difficulties I see.

 

1) The ADC output gives 32-bits at 750MHz, are the LVDSs capable of this speed?

2) Is it possible to push this much data over the Zynq's High performance AXI slave port towards the DDR?

3) The internal PL also needs also to run at 750MHz, this seams like a lot, is this possible?

 

The idea is to make a very high speed oscilloscope with long sample logging time (hence the external DDR memory). A basic ADC data path is described in the attached PNG file.

 

Any thoughts on the above?

Oscilloscope basic idea.PNG
0 Kudos
6 Replies
Highlighted
Teacher
Teacher
7,498 Views
Registered: ‎03-31-2012

Re: Interfacing an 3 Gsps ADC ADC08D1520 at 750Mhz

1) Yes
2) No Max bandwidth of HPx is 600 MB/s which is less than 3G/4. Also how much ddr bandwidth do you have?
3) No but you maybe able to use ISERDES to do /2, /4 rate output which might work.

What you are suggesting is quite challenging. You most probably don't have enough usable bandwidth. You might want to do some compression first.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
0 Kudos
Highlighted
Teacher
Teacher
7,485 Views
Registered: ‎07-09-2009

Re: Interfacing an 3 Gsps ADC ADC08D1520 at 750Mhz

agree with muzaffer, 

 

also have you looked at how much data you want to save,

    zynq is limited in its amount of DDR on the zynq port,

        putting a second ddr port on the PL , just for the adc samples bulk store gives you more at higher difficulty

 

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
Visitor
Visitor
7,372 Views
Registered: ‎06-02-2016

Re: Interfacing an 3 Gsps ADC ADC08D1520 at 750Mhz

Hi All,

 

Thanks for your replys.

 

We use the 32-bit DDR interface from the zynq to interface to 1GB of DDR memory (2x 512 chip)

 

Is it possible to combine 2 HPx slave ports into a 128 bits wide port? This way I could reduce the PL clock speed by 4 and allow for sub 250MHz operation. Basic idea is again added in the attached file.

Idea is to buffer 4 x 32 bits at 750Mhz and pass this to a sub 250MHz 128 bits AXI bus. Somehow combining 2 AXI HP slave interfaces into 1 virtual 128 bits wide axi HP bus. This data is then passed to the DDR memory via the Zynq DDR controller.

 

One goal of the project is to save as much data as possible so using data compression is not the first though. Also adding a second DDR controller is not possible as we do not have enough pins available. We we need a much bigger package. The adc interface is already using 34 LVDS pairs (=68 IOs)

 

Please feel free to comment on the above proposed solution. And if you have any other thoughts they are all welkom.

Oscilloscope basic data path (no triggering).PNG
0 Kudos
Highlighted
Teacher
Teacher
7,366 Views
Registered: ‎03-31-2012

Re: Interfacing an 3 Gsps ADC ADC08D1520 at 750Mhz

with 32 bit ddr at ~500 MHz, you have max 4GB/s bandwidth, with probably not much more than 3GB/s usable. So it's tight to start with.

Even with 2 HP ports your max bandwidth is probably 2*600 MB/s = 1.2GB/s.
So 3Gsps at 8 bits looks not feasible.

>> One goal of the project is to save as much data as possible so using data compression is not the first though.

I am not exactly clear what this sentence is saying but to me it seems that it's making contradictory statements. If you want to save as much data, you do want to do compression. You have only 1G to begin with (ie only 300 ms of data saved) so you can save little data without compression. Even a lossless compression scheme might allow you to double that relatively easily.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
0 Kudos
Highlighted
Teacher
Teacher
7,362 Views
Registered: ‎07-09-2009

Re: Interfacing an 3 Gsps ADC ADC08D1520 at 750Mhz

rather than use 128 bit data , 

    use mutliple streams / fifos between the  PL and PS, and ping pong, 

         the AXI has a terrible single word access time, not bad bursts.

 

1 G of memory is not a lot to store data, 

     and the zynq can't support more natively,

 

and with the zynq using some of the bandwidth of the ddr, your on a hiding to nothing

 

You ask for thoughts

 

Your using a USD 800 plus ADC,

 

"its the wrong FPGA "...

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
Highlighted
Newbie
Newbie
1,057 Views
Registered: ‎04-18-2018

Re: Interfacing an 3 Gsps ADC ADC08D1520 at 750Mhz

I saw this message looking for other info. I realize the original is 2 years old, but perhaps others may benefit from this post.

 

I am working on a project using three ADCADC08D1520 ADCs operating at 8b 1.5GSPS with 2-channels (I&Q) interfacing to an XC7VX485T. Each of the 2-ADC channel inputs is 4-sample lanes, 8b each, for 32b of data every 375MHz clock period (1.5GHz/4). 2-ADC 8b sample lanes of channel-1 are valid on the rising edge of the clock, the other 2 on the falling, I.E. DDR rate of 750MHz. The 2nd ADC channel, Q, is captured identically to the 1st, I.

 

A Xilinx DDR receiver IP in the IO section of the FPGA is used for the data capture of the ADC's clocking at 375MHz. The 375MHz clock is from one of the ADCs and is used to create the FPGA fabric system clock at 375MHz. The clock domain crossing is accomplished via a FIFO with input at the ADC's clock and output at the fabric system clock.

 

So the fabric sees 4-lanes of data from each ADC channel every 2.7ns. I wonder if your application could use this front end sampler to store your samples in parallel at a reasonable clock rate.

 

0 Kudos